Mask pattern generating method

• US 7,541,117 B2
• Filed: 04/16/2007
• Issued: 06/02/2009
• Est. Priority Date: 04/18/2006
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Ogawa, Kazuhisa, Nakamura, Satomi, Nakayama, Kohichi
• Primary Examiner(s): Wells; Nikita
• Assistant Examiner(s): Smith; Johnnie L
• Application Number:
  US11/735,778
• Publication Number:
  US 20070283313A1
• Time in Patent Office: 778 Days
• Field of Search: 430/5, 430/313, 430/311, 430/312, 430/394, 430/396
• US Class Current: 430/5
• CPC Class Codes: G03F 1/30 Alternating PSM, e.g. Levenson-Shibuya PSM; Preparation thereof
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 21/32139 using masks

Abstract

Disclosed herein is a mask pattern generating method for generating a mask pattern to be formed in a Levenson phase shift mask used in a light exposure process for exposing a photoresist film formed on a fabricated film to be patterned into a conductive layer to light when the conductive layer is patterned by photolithography, the conductive layer including a gate electrode formed in an active region extending in a first direction in a wafer in such a manner as to extend in a second direction orthogonal to the first direction, the mask pattern generating method including: a phase shifter arranging step; a shifter pattern image obtaining step; a trim pattern image obtaining step; and a phase shifter elongating step.

Claims

1. A mask pattern generating method for generating a mask pattern to be formed in a Levenson phase shift mask used in a light exposure process for exposing a photoresist film formed on a fabricated film to be patterned into a conductive layer to light when said conductive layer is patterned by photolithography, said conductive layer including a gate electrode formed in an active region extending in a first direction in a wafer in such a manner as to extend in a second direction orthogonal to said first direction, said mask pattern generating method comprising the steps of:

arranging, in said first direction, a plurality of phase shifters producing a shifter pattern image by being illuminated as said mask pattern at an interval such that said gate electrode is interposed between said phase shifters;

obtaining the shifter pattern image transferred to said photoresist film when the Levenson phase shift mask in which said phase shifters are arranged in said phase shifter arranging step is illuminated;

obtaining a trim pattern image transferred to said photoresist film when a trim mask in which a trim pattern is disposed so as to correspond to said conductive layer is illuminated; and

elongating said phase shifters arranged in said phase shifter arranging step in a direction of going away from a side of said gate electrode in said second direction;

wherein said phase shifter elongating step elongates said phase shifters arranged in said phase shifter arranging step to a position in the direction of going away from the side of said gate electrode in said second direction such that the shifter pattern image obtained in said shifter pattern image obtaining step and the trim pattern image obtained in said trim pattern image obtaining step do not overlap each other.

2. The mask pattern generating method as claimed in claim 1, further comprising the step of comparing the shifter pattern image obtained in said shifter pattern image obtaining step with pattern shape of said phase shifters arranged in said phase shifter arranging step in a region corresponding to said active region,

wherein when a result of comparison in said comparing step indicates that the shifter pattern image obtained in said shifter pattern image obtaining step differs from the pattern shape of said phase shifters arranged in said phase shifter arranging step in the region corresponding to said active region, said phase shifter elongating step elongates said phase shifters arranged in said phase shifter arranging step.

3. The mask pattern generating method as claimed in claim 2, further comprising the steps of:

calculating contact positions at which outlines of said shifter pattern image obtained in said shifter pattern image obtaining step and said trim pattern image obtained in said trim pattern image obtaining step come into contact with each other in said first direction and said second direction when said trim pattern image is moved in said first direction and said second direction to said shifter pattern image, and calculating regions where said trim pattern is allowed to overlap said phase shifters arranged in said phase shifter arranging step as overlap allowing regions on a basis of a result of the calculated contact positions; and

arranging said overlap allowing regions calculated in said overlap allowing region calculating step such that edge parts in said second direction of said overlap allowing regions correspond to edge parts in said second direction of said phase shifters arranged in said phase shifter arranging step;

wherein said phase shifter elongating step elongates said phase shifters arranged in said phase shifter arranging step when regions where said trim pattern overlaps said phase shifters in which said overlap allowing regions are arranged in said overlap allowing region arranging step do not include a region other than said overlap allowing regions.

4. The mask pattern generating method as claimed in claim 3, further comprising the step of shortening a phase shifter elongated in said phase shifter elongating step in a direction of approaching the side of said gate electrode when a region where said trim pattern overlaps said phase shifter elongated in said phase shifter elongating step include a region other than said overlap allowing regions.