Method of aligning deposited nanotubes onto an etched feature using a spacer

• US 7,541,216 B2
• Filed: 12/14/2005
• Issued: 06/02/2009
• Est. Priority Date: 06/09/2005
• Status: Active Grant

• Current Assignee: Nantero Incorporated
• Original Assignee: Nantero Incorporated
• Inventors: Neville, Christopher L., Yates, Colin D.
• Primary Examiner(s): Nguyen; Ha Tran
• Assistant Examiner(s): Tillie; Chakila
• Application Number:
  US11/304,871
• Publication Number:
  US 20060281287A1
• Time in Patent Office: 1,266 Days
• Field of Search: 438/99, 438/286, 438/303, 438/585, 438/596, 257/40
• US Class Current: 438/99
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/53276 containing carbon, e.g. fullerenes superconducting fullerenes H10N60/853
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature. The spacers are etched until the sidewalls of the raised feature are exposed forming a notched feature at the top of the spacers. A patterned nanotube layer is formed such that the nanotube layer overlies the top of the spacer and contacts a side portion of the raised feature in the notched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.

Claims

1. A method of forming a nanotube connection aligned to an etched feature, the method comprising:

forming a raised feature on a substrate surface, the feature including a top surface and sides;

forming a spacer on a side of the raised feature, the spacer being shorter than the raised feature so that the top portion of the raised feature extends above the top of the spacer and a portion of the side of the raised feature is exposed thereby defining a notched region above the spacer and adjacent to the top portion of the raised feature;

depositing and patterning a nanotube layer on the substrate such that the nanotube layer is deposited in the notched region and contacts the exposed portion of the raised feature and overlaps a portion of the top of the raised feature;

forming an insulating layer on the substrate that covers the nanotube layer; and

removing a top portion of the insulating layer to expose a top portion of the etched feature and removing the nanotube layer from on top of the etched feature leaving a portion of the nanotube layer in contact with the etched feature.

2. The method of claim 1 wherein the raised feature comprises raised metal layer.

3. The method of claim 2 wherein the raised metal layer is formed using an anisotropic process.

4. The method of claim 1 wherein the spacers is formed by:

depositing a first layer of electrically insulating material on the substrate covering at least a portion of the top of the raised feature and covering the side of the raised feature;

etching the first layer of electrically insulating material such that the insulating material is removed from the top of the raised feature and the substrate and such that a portion of the first layer of electrically insulating material is etched to below the height of the raised feature forming a spacer and exposing a portion of the side of the raised feature forming a notched feature above the spacer;

and

wherein depositing and patterning a nanotube layer includes forming a nanotube layer such that the nanotube layer contacts portions of the side of the raised feature, the notched portion, and overlaps a portion of the top of the raised feature; and

wherein removing a top portion of the insulating layer exposes a top portion of the raised feature, removes the nanotube layer from on top of the raised feature, and leaves a portion of the nanotube layer overlapping a spacer in the notched feature, thereby insuring the nanotube layer remains in contact with the side of the raised feature.

5. The method of claim 4 wherein the etching of the first layer of electrically insulating material is conducted so that the notched feature extends downward exposing no more than half of the height of the side of the raised feature.

6. The method of claim 1 wherein the raised feature comprises a transistor gate stack.

7. The method of claim 1 wherein forming the raised feature comprises forming the raised feature with a sloped profile in the side of the raised feature;

and

wherein depositing and patterning a nanotube layer includes depositing a portion of the nanotube layer so that it contacts the exposed sloped side portion of the raised feature and overlaps a portion of the top of the raised feature.

8. The method of claim 1 wherein removing a top portion of the insulating layer is accomplished using chemical mechanical polishing.

9. The method of claim 1 wherein removing a top portion of the insulating layer is accomplished using etching.

10. The method of claim 1 wherein forming the raised feature comprises forming a raised metal-containing feature by depositing metal-containing materials on the substrate.

11. The method of claim 10 wherein depositing metal-containing materials comprises depositing a layer of material selected from among aluminum, tungsten, tantalum, and titanium.

12. The method of claim 10 wherein depositing metal-containing materials comprises depositing metal alloys.

13. The method of claim 10 wherein depositing metal-containing materials comprises depositing metal nitrides.

14. The method of claim 10 wherein depositing metal-containing materials comprises depositing more than one layer of metal-containing material.