Methods for reducing within chip device parameter variations

• US 7,541,613 B2
• Filed: 05/08/2008
• Issued: 06/02/2009
• Est. Priority Date: 05/10/2006
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Rankin, Jed Hickory, Butt, Shahid Ahmad, Lindo, Patrick Edward, Nowak, Edward Joseph, Anderson, Brent Alan, Gabor, Allen H.
• Primary Examiner(s): Thai; Luan C
• Application Number:
  US12/117,014
• Publication Number:
  US 20080246097A1
• Time in Patent Office: 390 Days
• Field of Search: 257/48, 257/E21.524, 438/11, 438/14, 438/18
• US Class Current: 257/48
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.

Claims

1. An integrated circuit chip, comprising:

a multiplicity of virtual regions, at least two or more of said virtual regions having identically designed field effect transistors;

a reflectivity of light of a first region of said two or more virtual regions different from a reflectivity of light of a second region of said two or more virtual regions;

first field effect transistors in said first region of said two or more virtual regions having physical polysilicon gate lengths that are different from physical polysilicon gate lengths of second field effect transistors in said second region of said two or more virtual regions, said first and second field effect transistors identically designed; and

wherein a value of a functional device parameter of said first field effect transistors in said first region of said two or more virtual regions is the same as a value of a same functional device parameter of said second field effect transistors in said second region of said two or more virtual regions.

2. The integrated circuit chip of claim 1, wherein said functional device parameter is selected from the group consisting of threshold voltage, source-to-drain resistance and gate polysilicon sheet resistance.

3. The integrated circuit chip of claim 1, wherein said first and second field effect transistors have a lower threshold voltage than a nominal threshold voltage of otherwise identical nominal threshold voltage field effect transistors of said integrated circuit.

4. The integrated circuit chip of claim 1, wherein said first and second field effect transistors have a higher threshold voltage than a nominal threshold voltage of otherwise identical nominal threshold voltage field effect transistors of said integrated circuit.

5. The integrated circuit chip of claim 1, wherein said first and second field effect transistors have a gate dielectric thickness that is less than a gate dielectric thickness of otherwise identical nominal gate dielectric thickness field effect transistors of said integrated circuit.

6. The integrated circuit chip of claim 1, wherein said first and second field effect transistors have a gate dielectric thickness that is greater than a gate dielectric thickness of otherwise identical nominal gate dielectric thickness field effect transistors of said integrated circuit.

7. An integrated circuit chip, comprising:

a multiplicity of virtual regions, at least two or more of said virtual regions having identically designed field effect transistors, a reflectivity of light of a first region of said two or more virtual regions different from a reflectivity of light of a second region of said two or more virtual regions; and

first field effect transistors in said first of said two or more virtual regions having metallurgical polysilicon gate lengths that are different from metallurgical polysilicon gate lengths of second field effect transistors in said second region of said two or more virtual regions, said first and second field effect transistors identically designed,

wherein a value of a functional device parameter of said first field effect transistors in said first region of said two or more virtual regions is the same as a value of a same functional device parameter of said second field effect transistors in said second region of said two or more virtual regions.

8. The integrated circuit chip of claim 7, wherein said functional device parameter is selected from the group consisting of threshold voltage, source-to-drain resistance and gate polysilicon sheet resistance.

9. The integrated circuit chip of claim 7, wherein said first and second field effect transistors have a lower threshold voltage than a nominal threshold voltage of otherwise identical nominal threshold voltage field effect transistors of said integrated circuit.

10. The integrated circuit chip of claim 7, wherein said first and second field effect transistors have a higher threshold voltage than a nominal threshold voltage of otherwise identical nominal threshold voltage field effect transistors of said integrated circuit.

11. The integrated circuit chip of claim 7, wherein said first and second field effect transistors have a gate dielectric thickness that is less than a gate dielectric thickness of otherwise identical nominal gate dielectric thickness field effect transistors of said integrated circuit.

12. The integrated circuit chip of claim 7, wherein said first and second field effect transistors have a gate dielectric thickness that is greater than a gate dielectric thickness of otherwise identical nominal gate dielectric thickness field effect transistor of said integrated circuit.

13. The integrated circuit of claim 7, wherein said first field effect transistors have a first source/drain junction profile that is different from a second source/drain junction profile of said second field effect transistors.

14. The integrated circuit of claim 7, wherein said first field effect transistors have a first polysilicon gate sheet resistance that is different from a second polysilicon gate sheet resistance of said second field effect transistors.