High K-gate oxide TFTs built on transparent glass or transparent flexible polymer substrate

• US 7,541,626 B2
• Filed: 03/28/2006
• Issued: 06/02/2009
• Est. Priority Date: 03/28/2005
• Status: Expired due to Fees

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Tuller, Harry L., Kim, Il-Doo
• Primary Examiner(s): LEE, HSIEN MING
• Application Number:
  US11/391,034
• Publication Number:
  US 20060234852A1
• Time in Patent Office: 1,162 Days
• Field of Search: 438/82, 438/99, 438/287, 257/40, 257/262, 257/274, 257/E21.269, 257/E21.272, 313/504, 313/506, 428/690, 428/917
• US Class Current: 257/213
• CPC Class Codes: C04B 2235/3251 Niobium oxides, niobates, tantalum oxides, tantalates, or oxide-forming salts thereof
• CPC Class Codes: C04B 2235/3284 Zinc oxides, zincates, cadmium oxides, cadmiates, mercury oxides, mercurates or oxide forming salts thereof
• CPC Class Codes: C04B 2235/3294 Antimony oxides, antimonates, antimonites or oxide forming salts thereof, indium antimonate
• CPC Class Codes: C04B 2235/3298 Bismuth oxides, bismuthates or oxide forming salts thereof, e.g. zinc bismuthate
• CPC Class Codes: C04B 2235/76 Crystal structural characteristics, e.g. symmetry
• CPC Class Codes: C04B 2235/9653 Translucent or transparent ceramics other than alumina
• CPC Class Codes: C04B 35/01 based on oxide ceramics
• CPC Class Codes: C04B 35/495 based on vanadium, niobium, tantalum, molybdenum or tungsten oxides or solid solutions thereof with other oxides, e.g. vanadates, niobates, tantalates, molybdates or tungstates
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A transparent thin film transistor device includes a transparent substrate, and a high dielectric constant insulator layer disposed over the transparent substrate at a defined temperature. A transparent semiconductor layer is disposed over the insulator layer.

Claims

1. A transparent thin film transistor device comprising:

a transparent substrate;

a high dielectric constant insulator layer disposed over the transparent substrate at a defined temperature, said high dielectric constant insulator layer comprises at least one material selected from the group consisting of Bi₂(Zn_1/3Nb_2/3)₂O₇, Bi_1.5Zn_1.0M_1.5O₇ (M=Nb, Ta, Sb), (Bi)<sub>1˜

2</sub>(Zn, Nb, Ta, Ti)₂O₇, (Ca, Ba, Sr, Pb)<sub>1˜

2</sub>(Zn, Nb, Ta, Ti, Zr)₂O₇, and (Ca_1-xSr_x)Bi₄Ti₄O₁₅; and

a transparent semiconductor layer disposed over the high dielectric constant insulator layer.

2. The transistor device of claim 1, wherein the transparent substrate comprises glass, PET, PEN, PES, or Polyimide.

3. The transistor device of claim 1, wherein the high dielectric constant insulator layer is formed at least one process selected from the group consisting of sputtering, pulsed laser deposition, evaporation, chemical vapor deposition, and atomic layer deposition.

4. The transistor device of claim 1, wherein the high dielectric constant insulator layer is deposited at room temperature.

5. The transistor device of claim 1, wherein the high dielectric constant insulator layer is obtained below 300°

C. deposition.

6. The transistor device of claim 1, wherein the high dielectric constant insulator layer is annealed in air or oxygen atmosphere below 300°

C. following room temperature deposition.

7. The transistor device of claim 1, wherein the high dielectric constant insulator layer comprises a thickness no greater than approximately 2000 nm.

8. The transistor device of claim 1, wherein the high dielectric constant insulator layer comprises an amorphous or a nanocrystalline structure.

9. The transistor device of claim 1, wherein the high dielectric constant insulator layer comprises a high optical transmittance greater than 80%.

10. The transistor device of claim 1, wherein the high dielectric constant insulator layer comprises a capacitor structure for flexible embedded capacitor.

11. The transistor device of claim 1, wherein the transparent semiconductor layer comprises wide band gap oxide semiconductor where at least one material selected from the group consisting of ZnO, SnO2, In doped ZnO, and Ga doped ZnO.

12. The method of claim 1, wherein the transparent substrate comprises glass, PET, PEN, PES, or Polyimide.

13. A method of developing a transparent thin film transistor device comprising:

providing a transparent substrate;

forming a high dielectric constant insulator layer disposed over the transparent substrate at a defined temperature, said high dielectric constant insulator layer comprises at least one material selected from the group consisting of Bi₂(Zn_1/3Nb_2/3)₂O₇, Bi_1.5Zn_1.0M_1.5O₇ (M=Nb, Ta, Sb), (Bi)<sub>1˜

2</sub>(Zn, Nb, Ta, Ti)₂O₇, (Ca, Ba, Sr, Pb)<sub>1˜

2</sub>(Zn, Nb, Ta, Ti, Zr)₂O₇, and (Ca_1-xSr_x)Bi₄Ti₄O₁₅; and

forming a transparent semiconductor layer disposed over the high dielectric constant insulator layer.

14. The method of claim 13, wherein the high dielectric constant insulator layer is formed at least one process selected from the group consisting of sputtering, pulsed laser deposition, evaporation, chemical vapor deposition, and atomic layer deposition.

15. The method of claim 13, wherein the high dielectric constant insulator layer is deposited at room temperature.

16. The method of claim 13, wherein the high dielectric constant insulator layer is obtained below 300°

C. deposition.

17. The method of claim 13, wherein the high dielectric constant insulator layer is annealed in air or oxygen atmosphere below 300°

C. following room temperature deposition.

18. The method of claim 13, wherein the high dielectric constant insulator layer comprises a thickness no greater than approximately 2000 nm.

19. The method of claim 13, wherein the high dielectric constant insulator layer comprises an amorphous or a nanocrystalline structure.

20. The method of claim 13, wherein the high dielectric constant insulator layer comprises a high optical transmittance greater than 80%.

21. The method of claim 13, wherein the high dielectric constant insulator layer comprises a capacitor structure for flexible embedded capacitor.

22. The method of claim 13, wherein the transparent semiconductor comprises wide band gap oxide semiconductor where at least one material selected from the group consisting ZnO, SnO2, In doped ZnO, and Ga doped ZnO.