Embedded insulating band for controlling short-channel effect and leakage reduction for DSB process

• US 7,541,629 B1
• Filed: 04/21/2008
• Issued: 06/02/2009
• Est. Priority Date: 04/21/2008
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Luo, Zhijiong, Yin, Haizhou, Zhu, Huilong
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US12/106,658
• Time in Patent Office: 407 Days
• Field of Search: 257/19, 257/288, 257/301, 257/332, 257/347, 257/374, 257/401, 257/510, 257/520, 257/616, 257/622, 257/627, 438/198, 438/406, 438/424, 438/486
• US Class Current: 257/288
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method and structure for reducing leakage currents in integrated circuits based on a direct silicon bonding (DSB) fabrication process. After recessing a top semiconductor layer and an underlying semiconductor substrate, a dielectric layer may be deposited and etched back to form embedded spacers. Conventional source/drain regions may then be formed.

Claims

1. A semiconductor device comprising:

a silicon substrate having a first crystal orientation;

a silicon layer having a second crystal orientation, the silicon layer being bonded to a surface of the silicon substrate;

a gate structure formed over the silicon layer;

two recesses formed in the silicon layer and in the silicon substrate, the recesses defining two vertical sidewalls self-aligned to the gate structure, the sidewalls exposing an interface between the silicon layer and the silicon substrate;

two dielectric spacers, each dielectric spacer being formed on a respective sidewall and covering the exposed interface; and

two semiconducting regions, each semiconducting region being formed in a respective recess and embedding one of the dielectric spacers within the semiconductor device.