Memory cell comprising one MOS transistor with an isolated body having a reinforced memory effect

• US 7,541,636 B2
• Filed: 06/30/2006
• Issued: 06/02/2009
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: Stmicroelectronics Crolles 2 SAS (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Crolles 2 SAS (STMicroelectronics NV)
• Inventors: Mazoyer, Pascale, Ranica, Rossella, Villaret, Alexandre
• Primary Examiner(s): Phung; Anh
• Assistant Examiner(s): LULIS, MICHAEL P
• Application Number:
  US11/479,421
• Publication Number:
  US 20070013030A1
• Time in Patent Office: 1,068 Days
• Field of Search: 257/239, 257/E29.019, 257/314, 257/E29.025, 438/294
• US Class Current: 257/314
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A memory cell with one transistor on a floating body region isolated by its lower surface by a junction. According to the present invention, the junction is non-planar and, for example, includes a protrusion directed towards the transistor surface.

Claims

1. A memory cell with one transistor on a floating body region isolated by its lower surface by a junction, in which said junction is non-planar, further comprising an isolating ring around the floating body region, the isolating ring having an upper portion with a first width and a lower portion with a second width that is less than the first width, wherein said junction exhibits a peripheral upward protrusion at a level of the lower portion of the isolating ring.

2. A method for manufacturing the memory cell of claim 1, comprising the steps of:

forming first shallow openings and coating their lateral walls with spacers;

forming second deeper openings, using said spacers as a mask,

filling the openings, and

performing an implantation partially masked by the upper portion of the filled openings.

3. An integrated circuit comprising the memory cell of claim 1.

4. The memory cell of claim 1, wherein said junction comprises a protrusion directed towards the transistor surface.

5. The memory cell of claim 4, wherein said protrusion protrudes towards the gate substantially under the gate region of the transistor.

6. A method for manufacturing a memory cell with one transistor on a floating body region isolated by its lower surface by a junction, in which said junction is non-planar, wherein said junction comprises a protrusion directed toward a transistor surface, wherein said protrusion protrudes toward a gate substantially under a gate region of the transistor, wherein said protrusion results from an implantation performed with a mask substantially complementary to a gate mask used to define the gate of the transistor.

7. A semiconductor memory cell comprising:

a buried layer of a first conductivity type on a substrate;

a floating body region of a second conductivity type on the buried layer, a junction between the floating body region and the buried layer being non-planar;

a transistor on the floating body region; and

an isolating ring around the floating body region, the isolating ring having an upper portion with a first width and a lower portion with a second width that is less than the first width, wherein the junction is located at a level of the lower portion of the isolating ring.

8. A semiconductor memory cell as defined in claim 7, wherein the junction comprises a protrusion directed toward the transistor.

9. A semiconductor memory cell as defined in claim 8, wherein the transistor includes a gate region and wherein the protrusion is located under the gate region of the transistor.

10. A method for manufacturing a semiconductor memory cell, comprising:

forming a buried layer of a first conductivity type on a substrate;

forming a floating body region of a second conductivity type on the buried layer;

forming a non-planar junction between the floating body region and the buried layer; and

forming a transistor on the floating body region; and

forming an isolating ring around the floating body region, the isolating ring having an upper portion with a first width and a lower portion with a second width less than the first width, wherein the non-planar junction is formed at a level of the lower portion of the isolating ring.

11. A method as defined in claim 10, wherein forming an isolating ring comprises:

forming first shallow openings and coating their lateral walls with spacers;

forming second deeper openings using the spacers as a mask;

filling the first and second openings; and

performing an implantation partially masked by an upper portion of the filled openings.

12. A method as defined in claim 10, wherein forming a non-planar junction comprises forming a junction having a protrusion directed toward the transistor.

13. A method as defined in claim 12, wherein the transistor has a gate region and wherein forming a non-planar junction comprises forming the protrusion under the gate region of the transistor.

14. A method as defined in claim 12, wherein forming a non-planar junction comprises implantation through a mask.

15. A method as defined in claim 14, wherein the mask is complementary to a mask used to form a gate of the transistor.