Vertical field-effect transistor and method of forming the same
First Claim
1. A method of forming a semiconductor device, comprising:
- forming a vertical field-effect transistor, including;
forming a heavily doped substrate,forming a channel layer above said heavily doped substrate,forming a heavily doped source/drain layer above said channel layer,forming a source/drain contact above said heavily doped source/drain layer,patterning and etching pillar regions through said source/drain contact, said heavily doped source/drain layer, and portions of said channel layer to form a vertical cell,forming non-conductive regions in said portions of said channel layer within said pillar regions, andforming a gate above said non-conductive regions in said pillar regions; and
forming a Schottky diode, including;
forming a trench through said heavily doped substrate to said channel layer outside of said vertical cell and said pillar regions, andforming a contact below said heavily doped substrate within said vertical cell and pillar regions and within said trench, said contact within said vertical cell and pillar regions providing another source/drain contact for said vertical field-effect transistor, said contact within said trench providing an anode configured to cooperate with said channel layer that provides a cathode for said Schottky diode.
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Abstract
A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes a heavily doped source/drain layer above the channel layer and another source/drain contact above the heavily doped source/drain layer. The semiconductor device further includes pillar regions through the another source/drain contact, the heavily doped source/drain layer, and portions of the channel layer to form a vertical cell therebetween. Non-conductive regions of the semiconductor device are located in the portions of the channel layer within the pillar regions. The semiconductor device still further includes a gate above the non-conductive regions in the pillar regions. The semiconductor device may also include a Schottky diode including the channel layer and a Schottky contact.
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Citations
30 Claims
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1. A method of forming a semiconductor device, comprising:
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forming a vertical field-effect transistor, including; forming a heavily doped substrate, forming a channel layer above said heavily doped substrate, forming a heavily doped source/drain layer above said channel layer, forming a source/drain contact above said heavily doped source/drain layer, patterning and etching pillar regions through said source/drain contact, said heavily doped source/drain layer, and portions of said channel layer to form a vertical cell, forming non-conductive regions in said portions of said channel layer within said pillar regions, and forming a gate above said non-conductive regions in said pillar regions; and forming a Schottky diode, including; forming a trench through said heavily doped substrate to said channel layer outside of said vertical cell and said pillar regions, and forming a contact below said heavily doped substrate within said vertical cell and pillar regions and within said trench, said contact within said vertical cell and pillar regions providing another source/drain contact for said vertical field-effect transistor, said contact within said trench providing an anode configured to cooperate with said channel layer that provides a cathode for said Schottky diode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A semiconductor device, comprising:
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a vertical field-effect transistor, including; a heavily doped substrate, a channel layer above said heavily doped substrate, a heavily doped source/drain layer above said channel layer, a source/drain contact above said heavily doped source/drain layer, pillar regions including said source/drain contact, said heavily doped source/drain layer, and portions of said channel layer to form a vertical cell therebetween, non-conductive regions in said portions of said channel layer within said pillar regions, and a gate above said non-conductive regions in said pillar regions; and a Schottky diode, including; a contact below said heavily doped substrate within said vertical cell and pillar regions and within a trench through said heavily doped substrate to said channel layer outside of said vertical cell and said pillar regions, said contact within said vertical cell and pillar regions providing another source/drain contact for said vertical field-effect transistor, said contact within said trench providing an anode configured to cooperate with said channel layer that provides a cathode for said Schottky diode. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A power converter coupled to a source of electrical power and configured to provide a regulated output characteristic, comprising:
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a semiconductor device, including; a power switch formed as a vertical field-effect transistor, including; a heavily doped substrate, a channel layer above said heavily doped substrate, a heavily doped source/drain layer above said channel layer, a source/drain contact above said heavily doped source/drain layer, pillar regions including said source/drain contact, said heavily doped source/drain layer, and portions of said channel layer to form a vertical cell therebetween, non-conductive regions in said portions of said channel layer within said pillar regions, and a gate above said non-conductive regions in said pillar regions, and a Schottky diode, including; a contact below said heavily doped substrate within said vertical cell and pillar regions and within a trench through said heavily doped substrate to said channel layer outside of said vertical cell and said pillar regions, said contact within said vertical cell and pillar regions providing another source/drain contact for said vertical field-effect transistor, said contact within said trench providing an anode configured to cooperate with said channel layer that provides a cathode for said Schottky diode; a controller configured to control conduction intervals of said power switch to provide said regulated output characteristic; and an output filter coupled to said power switch to filter said output characteristic. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
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Specification