Semiconductor integrated circuit

• US 7,541,651 B2
• Filed: 08/02/2006
• Issued: 06/02/2009
• Est. Priority Date: 08/02/2005
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Sumita, Masaya
• Primary Examiner(s): Purvis, Sue A.
• Assistant Examiner(s): YEUNG LOPEZ, FEIFEI
• Application Number:
  US11/497,514
• Publication Number:
  US 20070085146A1
• Time in Patent Office: 1,035 Days
• Field of Search: None
• US Class Current: 257/371
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor integrated circuit has a first substrate of a first polarity to which a first substrate potential is given, a second substrate of the first polarity to which a second substrate potential different from the first substrate potential is given, and a third substrate of a second polarity different from the first polarity. The first substrate is insulated from a power source or ground to which a source of a MOSFET formed on the substrate is connected. The third substrate is disposed between the first and second substrates in adjacent relation to the first and second substrates. A circuit element is formed on the third substrate.

Claims

1. A semiconductor integrated circuit comprising:

a substrate;

a first well of a first polarity to which a first potential is given;

a second well of the first polarity to which a second potential different from the first potential is given;

a third well of a second polarity different from the first polarity;

a fourth well of the second polarity, which is above the substrate; and

a circuit element on the third well, wherein

the first well is insulated from a power source or ground to which a source of a MOSFET formed on the first well is connected,

the third well is disposed between the first and second wells in adjacent relation to the first and second wells, and

the first well, the second well and the third well are above the fourth well.

2. The semiconductor integrated circuit of claim 1, wherein the circuit element is a MOSFET.

3. The semiconductor integrated circuit of claim 1, wherein the circuit element is a high-resistance load element.

4. The semiconductor integrated circuit of claim 3, wherein the high-resistance load element is formed of polysilicon or a diffused layer.

5. The semiconductor integrated circuit of claim 1, wherein the second well is isolated from a power source or ground to which a source of a MOSFET formed on the second well is connected.

6. The semiconductor integrated circuit of claim 1, wherein the third well is isolated from a power source or ground to which a source of a MOSFET formed on the third well is connected.

7. The semiconductor integrated circuit of claim 1, wherein the first to third wells have respective MOSFETs provided thereon and the first to third wells form one cell.

8. The semiconductor integrated circuit of claim 1, wherein each of the first and second potentials is supplied from a potential generation circuit.

9. The semiconductor integrated circuit of claim 1, wherein the MOSFET formed on the first well and a MOSFET formed on the second well have different thresholds.

10. The semiconductor integrated circuit of claim 1, wherein a gate oxide film of the MOSFET formed on the first well and a gate oxide film of a MOSFET formed on the second well have different thicknesses.

11. The semiconductor integrated circuit of claim 1, wherein a gate oxide film of the MOSFET formed on the first well and a gate oxide film of a MOSFET formed on the second well are made of different materials.

12. The semiconductor integrated circuit of claim 1, further comprising:

a potential supply line for supplying the first potential, wherein

the potential supply line is provided on the first well and extending in a direction parallel with a longer edge of the first well.

13. The semiconductor integrated circuit of claim 1, further comprising:

a potential supply line for supplying the second potential, wherein

the potential supply line is provided on the second well and extending in a direction parallel with a longer edge of the second well.

14. The semiconductor integrated circuit of claim 1, further comprising:

a potential supply line for supplying the first potential, wherein

the potential supply line is provided on the first well and extending in a direction parallel with a shorter edge of the first well.

15. The semiconductor integrated circuit of claim 1, further comprising:

a potential supply line for supplying the second potential, wherein

the potential supply line is provided on the second well and extending in a direction parallel with a shorter edge of the second well.

16. The semiconductor integrated circuit of claim 1, wherein the power source or ground line to which the source of the MOSFET formed on the first well is connected is different from a power source or a ground line to which a source of a MOSFET formed on the second well is connected.

17. The semiconductor integrated circuit of claim 1, wherein

an inversion diffused layer for supplying a potential to the third well is provided on the third well and

the inversion diffused layer is provided in a vicinity of the first well or the second well.

18. The semiconductor integrated circuit of claim 17, wherein the inversion diffused layer is provided in the vicinity of the one of the first and second wells to which the higher potential is given.

19. The semiconductor integrated circuit of claim 1, wherein a first MOSFET is formed on either one of the first and second wells and the first MOSFET has a gate and a drain each connected to the one of the first and second wells.

20. The semiconductor integrated circuit of claim 19, wherein the first MOSFET is formed on the one of the first and second wells to which the higher potential is given.

21. The semiconductor integrated circuit of claim 1, further comprising:

a fourth well surrounding a periphery of the second well, wherein

the fourth well is connected to a ground line.

22. The semiconductor integrated circuit of claim 7, further comprising:

a clock signal line;

a data input signal line; and

first and second signal lines, wherein

the MOSFET on the third well pre-charges the first signal line in response to a clock signal from the clock signal line,

the MOSFET on the first well discharges the first signal line in response to a data input signal from the data input signal line, and

the MOSFET on the second well discharges the second signal line in response to an output from the first signal line.

23. The semiconductor integrated circuit of claim 1, wherein

two or more series-connected MOSFETs, each for discharging a signal line, are formed on the second well and

a potential supply line or an inversion diffused layer each for supplying a potential to the third well is closer to the second well than to the wells of the first polarity other than the second well.

24. The semiconductor integrated circuit of claim 11, wherein

a MOSFET for discharging a first signal line in response to a clock signal is formed on the first well and

two or more series-connected MOSFETs, each for discharging a second signal line, are formed on the second well.

25. The semiconductor integrated circuit of claim 12, wherein

a MOSFET for discharging a first signal in response to a clock signal is formed on the first well and

two or more series-connected MOSFETs, each for discharging a second signal line, are formed on the second well.

26. The semiconductor integrated circuit of claim 1, wherein

a MOSPET for discharging a signal line in response to a clock signal is formed on either of the first and second wells of the first polarity and a potential at the well formed with the MOSFET has negative temperature dependence.

27. The semiconductor integrated circuit of claim 11, wherein

a MOSFET for discharging a signal line in response to a clock signal is formed on either of the first and second wells of the first polarity and a potential at the well formed with the MOSFET has negative temperature dependence.

28. The semiconductor integrated circuit of claim 1, further comprising:

a NAND circuit and a NOR circuit which are implemented with CMOS logic, wherein

NMOS transistors constituting the NOR circuit are formed on the first well and

NMOS transistors constituting the NAND circuit are formed on the second well.

29. The semiconductor integrated circuit of claim 1, wherein

a circuit in which NMOS transistors are connected in parallel is formed on the first well and

a circuit in which NMOS transistors are connected in series is formed on the second well.