Method and apparatus for power savings in a switching regulator

• US 7,541,790 B2
• Filed: 06/09/2006
• Issued: 06/02/2009
• Est. Priority Date: 06/09/2006
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Webb, Richard B., Schopfer, Walter S.
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US11/450,790
• Publication Number:
  US 20070285069A1
• Time in Patent Office: 1,089 Days
• Field of Search: 323/281, 323/282, 323/283, 323/284, 323/285, 323/351
• US Class Current: 323/282
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

In one embodiment, the present invention includes a regulator having a pulse width modulation (PWM) controller to generate a PWM control signal based on a voltage level of a load coupled to the regulator, a driver to provide a drive signal to a switching element of the regulator responsive to the PWM control signal, and a power saver coupled between the PWM controller and the driver to receive the PWM control signal and to output the PWM control signal to the driver at a reduced rate during an idle mode of the load.

Claims

1. A voltage regulator:

a pulse width modulation (PWM) controller to generate a PWM control signal based on a voltage level of a load coupled to the voltage regulator;

a driver to provide a drive signal to a switching element of the voltage regulator responsive to the PWM control signal; and

a power saver coupled between the PWM controller and the driver to receive the PWM control signal and to output the PWM control signal to the driver at a reduced rate during an idle mode of the load, wherein the power saver is to receive an enable signal from the load during the idle mode and comprises a logic circuit including;

a counter to receive a clock signal and generate a counter output; and

circuitry to receive the counter output, the enable signal, and the PWM control signal and to output the PWM control signal at the reduced rate.

2. The voltage regulator of claim 1, wherein the power saver is to output the PWM control signal at a full rate during a normal mode of the load.

3. The voltage regulator of claim 1, wherein the counter comprises a Johnson counter.

4. The voltage regulator of claim 1, wherein the counter is to control output of the PWM control signal to the driver during the idle mode and the PWM controller is to control output of the PWM control signal to the driver during the normal mode.

5. The voltage regulator of claim 1, wherein the logic circuit is to output the PWM control signal at the reduced rate corresponding to one pulse per N pulses of the PWM control signal.

6. A system comprising:

a voltage regulator including;

a switching element controlled by a drive signal, wherein the drive signal is controlled by a duty cycle controller; and

power saving means coupled to the duty cycle controller to reduce a rate at which the duty cycle controller controls the drive signal, comprising a counter to receive a clock signal and generate a counter output based thereon and logic circuitry to receive the counter output, the enable signal, and a duty cycle signal and to output the duty cycle signal at the reduced rate; and

a circuit coupled to the voltage regulator to be powered by the voltage regulator, wherein the circuit is operable at least at a first load level and a second load level higher than the first load level, wherein the circuit is to send an enable signal to the power saving means when operating at the first load level and to not send the enable signal when operating at the second load level.

7. The system of claim 6, wherein the first load level comprises an idle mode.

8. The system of claim 6, wherein the power saving means is to receive a duty cycle signal from the duty cycle controller and to pass one of every N pulses of the duty cycle signal to a driver coupled to provide the drive signal to the switching element.