Isolation circuit

• US 7,541,825 B2
• Filed: 09/28/2006
• Issued: 06/02/2009
• Est. Priority Date: 09/28/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Cram, Daniel P., Attalla, Hani S.
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): Nguyen; Tung X
• Application Number:
  US11/529,062
• Publication Number:
  US 20080191728A1
• Time in Patent Office: 978 Days
• Field of Search: 324/763, 324/760, 324/765, 324/158.1, 324/769, 327/77, 327/87, 327205-206, 438 14- 18, 257/48
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present disclosure includes various method, device, and system embodiments for isolation circuits. One such isolation circuit embodiment includes: a first transistor having its source connected to a first terminal, wherein the first terminal connects a supply voltage to the source of the first transistor; a register connected to the drain of the first transistor; and a second transistor in parallel with a resistor, the gate of the second transistor is connected to an output of the register and a source of the second transistor is connected to the first terminal. In various embodiments, the drain of the second transistor is connected to a second terminal and the state of the second transistor depends on whether the register is loaded.

Claims

1. An isolation circuit, comprising:

an on-die resistor stack having an input connected to a first voltage supply pad of a semiconductor die and an output signal connected to a second voltage supply pad of the semiconductor die, the first supply pad being connected to an external power supply, wherein the resistor stack includes a number of levels including;

a first level having a first resistor connected to a source of a first transistor, a gate of the first transistor being connected to a first enable input;

a second level having a second resistor connected to a source of a second transistor, a gate of the second transistor being connected to a second enable input; and

wherein the first and second enable inputs are controlled to set a resistance value of the resistor stack in order to limit a current value drawn by the die through the resistor stack during a testing operation.

2. The circuit of claim 1, wherein the first enable input is controlled by a first register and the second enable input is controlled by a second register in order to set the resistance value of the resistor stack.

3. The circuit of claim 1, wherein the first resistor is connected in series with the first transistor and the second resistor is connected in series with the second transistor.

4. The circuit of claim 3, wherein the first and second levels are parallel to each other.

5. The circuit of claim 3, wherein the resistor stack includes a third level that includes a third resistor connected to a source of a third transistor, a gate of the third transistor is connected to a third enable input.

6. The circuit of claim 1, wherein the second voltage supply pad is a built in self stress (BISS) supply pad and the testing operation is a BISS testing operation.

7. The circuit of claim 1, wherein the second voltage supply pad is a bum-in pad and the testing operation is a wafer level burn-in (WLB) testing operation.

8. The circuit of claim 1, wherein the resistance value of the resistor stack is set to a first value when the first voltage supply pad is shorted and is set to a different value when the first voltage supply pad is not shorted.