Method for correcting for asymmetry of threshold voltage shifts
First Claim
1. A method for correcting asymmetric threshold voltage shifts caused by negative-bias temperature instability (NBTI) during burn-in in an integrated circuit, the integrated circuit comprising a first signal path and a second signal path, each of the signal paths comprising a plurality of devices, a first device of the first signal path having a larger initial threshold voltage shift than a second device of the second signal path, the method comprising:
- scanning a first logic pattern into the first signal path, the first logic pattern causing bias conditions that induce recovery of the threshold voltage shift in the first device;
scanning a second logic pattern into the second signal path, the second logic pattern causing bias conditions that induce threshold voltage shift in the second device; and
operating the integrated circuit for a sufficient time to substantially equalize the threshold voltage shift of the first and second devices.
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Abstract
A method for correcting of asymmetric shifts in threshold voltage of transistors caused by effects such as negative-bias temperature instability (NBTI) during burn-in. The method may include providing logic patterns to an integrated circuit, such that devices that were stressed during burn-in are relaxed, and devices that suffered less stress during burn-in are stressed.
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Citations
1 Claim
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1. A method for correcting asymmetric threshold voltage shifts caused by negative-bias temperature instability (NBTI) during burn-in in an integrated circuit, the integrated circuit comprising a first signal path and a second signal path, each of the signal paths comprising a plurality of devices, a first device of the first signal path having a larger initial threshold voltage shift than a second device of the second signal path, the method comprising:
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scanning a first logic pattern into the first signal path, the first logic pattern causing bias conditions that induce recovery of the threshold voltage shift in the first device; scanning a second logic pattern into the second signal path, the second logic pattern causing bias conditions that induce threshold voltage shift in the second device; and operating the integrated circuit for a sufficient time to substantially equalize the threshold voltage shift of the first and second devices.
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Specification
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- Resources
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Current AssigneeInternational Business Machines Corporation
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Original AssigneeInternational Business Machines Corporation
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InventorsKueper, Terrance W., Bolam, Ronald J., Paulsen, David P., Sheets, John E. II
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Primary Examiner(s)PATEL, PARESH H
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Application NumberUS12/131,487Time in Patent Office365 DaysField of SearchNoneUS Class Current324/750.05CPC Class CodesG01R 31/2879 related to electrical aspec...
