Semi-static flip-flops for RFID tags
First Claim
Patent Images
1. A radio frequency identification (RFID) circuit, including:
- a first semi-static flip-flop having a first dynamic storage time and a first static storage time longer than the first dynamic storage time; and
a first timing block circuit operable to provide a first timing block clock signal to the first semi-static flip-flop, the first timing block clock signal having a first clock state duration shorter than the first dynamic storage time and a second clock state duration longer than the first dynamic storage time.
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Abstract
A radio frequency identification (RFID) circuit including a semi-static flip-flop having a static storage time longer than its dynamic storage time. The RFID circuit may include a timing block circuit to provide a timing block clock signal to the semi-static flip-flop, the signal having a first clock state duration shorter than the dynamic storage time and a second clock state duration longer than the dynamic storage time.
19 Citations
30 Claims
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1. A radio frequency identification (RFID) circuit, including:
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a first semi-static flip-flop having a first dynamic storage time and a first static storage time longer than the first dynamic storage time; and a first timing block circuit operable to provide a first timing block clock signal to the first semi-static flip-flop, the first timing block clock signal having a first clock state duration shorter than the first dynamic storage time and a second clock state duration longer than the first dynamic storage time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A radio frequency identification (RFID) tag, including:
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an antenna operable to receive a wireless signal having encoded symbols; a symbol detector operable to detect the encoded symbols of the wireless signal; a first semi-static flip-flop to couple to the symbol detector and having a first dynamic storage time and a first static storage time longer than the first dynamic storage time; and a first timing block circuit operable to provide a first timing block clock signal to the first semi-static flip-flop, the first timing block clock signal having a first clock state duration shorter than the first dynamic storage time and a second clock state duration longer than the first dynamic storage time. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A method, including:
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receiving a wireless signal at a radio frequency identification circuit; and clocking a semi-static flip-flop included in the radio frequency identification circuit with a timing block clock signal having a first clock state duration shorter than a first dynamic storage time of the semi-static flip-flop and a second clock state duration longer than the first dynamic storage time, wherein a first static storage time of the semi-static flip-flop is longer then the first dynamic storage time. - View Dependent Claims (25, 26, 27, 28, 29)
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30. An apparatus, including:
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means for receiving a wireless signal at a radio frequency identification circuit; and means for clocking a semi-static flip-flop included in the radio frequency identification circuit with a timing block clock signal having a first clock state duration shorter than a first dynamic storage time of the semi-static flip-flop and a second clock state duration longer than the first dynamic storage time, wherein a first static storage time of the semi-static flip-flop is longer then the first dynamic storage time.
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Specification