PLL circuit
First Claim
1. A PLL circuit comprising:
- a voltage controlled oscillator controlled by an analog control signal controlling an oscillation frequency over a first range and a digital control signal controlling the oscillation frequency over a range narrower than the first range;
a frequency comparison circuit comparing one of a frequency of an output of the voltage controlled oscillator and a frequency of a signal obtained by frequency-dividing the output of the voltage controlled oscillator; and
a frequency of a reference signal; and
a phase comparison circuit comparing one of a phase of the output of the voltage controlled oscillator and a phase of the signal obtained by frequency-dividing the output of the voltage controlled oscillator; and
a phase of the reference signal,wherein the PLL circuit is configured to control the oscillation frequency of the voltage controlled oscillator so that a frequency and a phase of one of the output of the voltage controlled oscillator and the signal obtained by frequency-dividing the output of the voltage controlled oscillator conform to the frequency and the phase of the reference signal,wherein a first circuit determining whether control of the oscillation frequency of the voltage controlled oscillator has reached a steady state is provided, andwherein at least one of a second circuit operating only when determination that the steady state has not been reached is made and a third circuit operating only when determination that the steady state has been reached is made is provided.
1 Assignment
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Accused Products
Abstract
Phase jitter of the hybrid control type PLL circuit in a steady state is reduced. A steady state detection circuit determining whether an output of a phase comparison circuit in the hybrid control type PLL circuit frequently changes is provided, determination that a steady state has not been reached is made if the output of the phase comparison circuit does not change for a while, determination that the steady state has been reached if the output of the phase comparison circuit frequently changes, and based on a result of the determination, a control width of controlling a oscillation frequency of a voltage controlled oscillator circuit by a digital control signal is changed or (and) a frequency of changing an analog control signal is changed. Thereby, a control width of the oscillation frequency by the digital control signal after reaching the steady state can be reduced without damaging convergence before reaching the steady state. Therefore, the phase jitter in the steady state can be reduced.
30 Citations
13 Claims
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1. A PLL circuit comprising:
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a voltage controlled oscillator controlled by an analog control signal controlling an oscillation frequency over a first range and a digital control signal controlling the oscillation frequency over a range narrower than the first range; a frequency comparison circuit comparing one of a frequency of an output of the voltage controlled oscillator and a frequency of a signal obtained by frequency-dividing the output of the voltage controlled oscillator; and
a frequency of a reference signal; anda phase comparison circuit comparing one of a phase of the output of the voltage controlled oscillator and a phase of the signal obtained by frequency-dividing the output of the voltage controlled oscillator; and
a phase of the reference signal,wherein the PLL circuit is configured to control the oscillation frequency of the voltage controlled oscillator so that a frequency and a phase of one of the output of the voltage controlled oscillator and the signal obtained by frequency-dividing the output of the voltage controlled oscillator conform to the frequency and the phase of the reference signal, wherein a first circuit determining whether control of the oscillation frequency of the voltage controlled oscillator has reached a steady state is provided, and wherein at least one of a second circuit operating only when determination that the steady state has not been reached is made and a third circuit operating only when determination that the steady state has been reached is made is provided. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification