Semiconductor memory device

• US 7,542,326 B2
• Filed: 08/13/2007
• Issued: 06/02/2009
• Est. Priority Date: 08/22/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Yoshimura, Satoshi, Sato, Shinichi, Yamagata, Satoru, Horii, Shinji
• Primary Examiner(s): Nguyen; Viet Q
• Application Number:
  US11/889,388
• Publication Number:
  US 20080049487A1
• Time in Patent Office: 659 Days
• Field of Search: 365/148, 365/171, 365/173, 365/158
• US Class Current: 365/148
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/883 Oxides or nitrides
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

A semiconductor memory device comprises an array of memory cells each comprising a variable resistance element and a cell access transistor, and a voltage supplying means for applying the first voltage between the bit and source lines connected to the selected memory cell, the third voltage to the word line to apply the first write voltage between the two ports of the variable resistance element for shifting the resistance from the first state to the second state, and the second voltage opposite in polarity to the first voltage between the bit and source lines, the third voltage to the word line to apply the second write voltage opposite in polarity to and different in the absolute value from the first write voltage between the two ports for shifting the resistance from the second state to the first state, the voltage supplying means comprising an n-channel MOSFET and a p-channel MOSFET.

Claims

1. A semiconductor memory device comprising:

an array of memory cells arranged in a row direction and a column direction, each memory cell including a series circuit of a variable resistance element having two-port structure and an electrically openable and closable switch electrically connected at one terminal to one port of the variable resistance element, each switch in the memory cells aligned along one row being connected at a control terminal to a common word line extending in the row direction, one port other than the control terminal of the memory cells aligned along one column being connected to a common bit line extending in the column direction, and the other port other than the control terminal of the memory cell being connected to a source line extending in the row or column direction; and

a voltage supplying means for conducting a first writing action for shifting an electrical resistance from a first state to a second state by applying a first voltage between the bit line and the source line connected to a selected memory cell to be written in the memory cell array and a third voltage to the word line connected to the control terminal of the switch in the selected memory cell thus to apply a first write voltage between the two ports of the variable resistance element in the selected memory cell, and for conducting a second writing action for shifting the electrical resistance from the second state to the first state by applying a second voltage, which is opposite in the polarity to the first voltage, between the bit line and the source line connected to the selected memory cell, and the third voltage to the word line connected to the control terminal of the switch in the selected memory cell thus to apply a second write voltage between the two ports of the variable resistance element in the selected memory cell, the second write voltage being opposite in the polarity to and different in the absolute value from the first write voltage, wherein

the variable resistance element is a nonvolatile memory element capable of storing information so that the information can be electrically written by shifting the electrical resistance between the first state and the second state when the first write voltage and the second write voltage are applied to the two ports respectively,

the switch is an element that shifts conductivity from a conductive state to a non-conductive state or vice versa between the first terminal and the second terminal according to a voltage applied to the control terminal, and

the voltage supplying means comprises an n-channel enhancement type MOSFET and a p-channel enhancement type MOSFET as drive elements for driving the source line.

2. The semiconductor memory device according to claim 1, wherein:

the memory cell includes a series circuit of a variable resistance element having two-port structure and an electrically openable and closable switch electrically connected at a first terminal to a second port of the variable resistance element,

each variable resistance element in the memory cells aligned along one column is connected at a first port to a common bit line extending in the column direction, and

the switch in the memory cell is connected at a second terminal to a source line extending in the row or column direction.

3. The semiconductor memory device according to claim 2, wherein

the switch is a cell access transistor comprising an enhancement type n-channel MOSFET, and

the first terminal, the second terminal, and the control terminal of the switch are a drain, a source, and a gate of the cell access transistor, respectively.

4. The semiconductor memory device according to claim 2, further comprising:

a readout circuit for detecting a current flowing along the bit line connected to the selected memory cell to be read out in the memory cell array and reading a memory state from the selected memory cell, wherein

in a reading action for reading the memory state from the selected memory cell, the voltage supplying means applies a fourth voltage between the bit line and the source line connected to the selected memory cell and then a fifth voltage to the word line connected to the control terminal of the switch in the selected memory cell for changing the switch into the conductive state, and the readout circuit detects a memory cell current which flows from the bit line to the source line connected to the selected memory cell though the variable resistance element and the switch in the selected memory cell according to the electrical resistance of the variable resistance element thus to read the memory state from the memory cell.

5. The semiconductor memory device according to claim 4, wherein the fifth voltage and the third voltage are identical to each other.

6. The semiconductor memory device according to claim 2, wherein the voltage supplying means uses the n-channel MOSFET or the p-channel MOSFET as the drive element by switching them between on and off according to whether it is in the first writing action or the second writing action.

7. The semiconductor memory device according to claim 2, wherein the first voltage and the second voltage are equal to each other in the absolute value.

8. The semiconductor memory device according to claim 2, wherein a potential at a high voltage side applied between the bit line and the source line connected to the selected memory cell is equal to a potential at the word line connected to the selected memory cell in at least either the first write action or the second write action.

9. The semiconductor memory device according to claim 2, wherein a potential at the word line connected to the selected memory cell is higher than a potential at a high voltage side applied between the bit line and the source line connected to the selected memory cell in at least either the first writing action or the second writing action.

10. The semiconductor memory device according to claim 2, wherein a potential at the low voltage side applied between the bit line and the source line connected to the selected memory cell is equal to a grounding potential in at least either the first writing action or the second writing action.

11. The semiconductor memory device according to claim 2, wherein a potential at a high voltage side applied between the bit line and the source line connected to the selected memory cell is equal between the first writing action and the second writing action.

12. The semiconductor memory device according to claim 2, wherein the first and second states of the electrical resistance in the variable resistance element are two of three or more resistance states which correspond to memory states of the variable resistance element, and an action of shifting the resistance state to other state than the first and second states is carried out by controlling a voltage level or an application time of the first voltage in the first writing action or the second voltage in the second writing action.

13. The semiconductor memory device according to claim 2, wherein the variable resistance element comprises a variable resistor which contains titanium nitride, titanium oxide, or titanium oxynitride.

14. The semiconductor memory device according to claim 2, wherein the variable resistance element comprises a variable resistor which contains a manganese-containing oxide having perovskite structure expressed by Pr₍₁₋

x)Ca_xMnO₃ (where 0<

x<

1).

15. The semiconductor memory device according to claim 1, wherein:

the memory cell includes a series circuit of a variable resistance element having two-port structure and an electrically openable and closable switch electrically connected at a second terminal to a second port of the variable resistance element,

each switch in the memory cells aligned along one column is connected at a first port to a common bit line extending in the column direction, and

the variable resistance element in the memory cell is connected at a first terminal to a source line extending in the row or column direction.

16. The semiconductor memory device according to claim 15, wherein

the switch is a cell access transistor comprising an enhancement type n-channel MOSFET, and

the first terminal, the second terminal, and the control terminal of the switch are a drain, a source, and a gate of the cell access transistor, respectively.

17. The semiconductor memory device according to claim 15, further comprising:

a readout circuit for detecting a current flowing along the bit line connected to the selected memory cell to be read out in the memory cell array and reading a memory state from the selected memory cell, wherein

in a reading action for reading the memory state from the selected memory cell, the voltage supplying means applies a fourth voltage between the bit line and the source line connected to the selected memory cell and then a fifth voltage to the word line connected to the control terminal of the switch in the selected memory cell for changing the switch into the conductive state, and the readout circuit detects a memory cell current which flows from the bit line to the source line connected to the selected memory cell though the variable resistance element and the switch in the selected memory cell according to the electrical resistance of the variable resistance element thus to read the memory state from the memory cell.

18. The semiconductor memory device according to claim 17, wherein the fifth voltage and the third voltage are identical to each other.

19. The semiconductor memory device according to claim 15, wherein the voltage supplying means uses the n-channel MOSFET or the p-channel MOSFET as the drive element by switching them between on and off according to whether it is in the first writing action or the second writing action.

20. The semiconductor memory device according to claim 15, wherein the first voltage and the second voltage are equal to each other in the absolute value.

21. The semiconductor memory device according to claim 15, wherein a potential at a high voltage side applied between the bit line and the source line connected to the selected memory cell is equal to a potential at the word line connected to the selected memory cell in at least either the first write action or the second write action.

22. The semiconductor memory device according to claim 15, wherein a potential at the word line connected to the selected memory cell is higher than a potential at a high voltage side applied between the bit line and the source line connected to the selected memory cell in at least either the first writing action or the second writing action.

23. The semiconductor memory device according to claim 15, wherein a potential at the low voltage side applied between the bit line and the source line connected to the selected memory cell is equal to a grounding potential in at least either the first writing action or the second writing action.

24. The semiconductor memory device according to claim 15, wherein a potential at a high voltage side applied between the bit line and the source line connected to the selected memory cell is equal between the first writing action and the second writing action.

25. The semiconductor memory device according to claim 15, wherein the first and second states of the electrical resistance in the variable resistance element are two of three or more resistance states which correspond to memory states of the variable resistance element, and an action of shifting the resistance state to other state than the first and second states is carried out by controlling a voltage level or an application time of the first voltage in the first writing action or the second voltage in the second writing action.

26. The semiconductor memory device according to claim 15, wherein the variable resistance element comprises a variable resistor which contains titanium nitride, titanium oxide, or titanium oxynitride.

27. The semiconductor memory device according to claim 15, wherein the variable resistance element comprises a variable resistor which contains a manganese-containing oxide having perovskite structure expressed by Pr₍₁₋

x)Ca_XMnO₃ (where 0<

x<

1).