Apparatus and method for calibrating the frequency of a clock and data recovery circuit

• US 7,542,533 B2
• Filed: 07/07/2005
• Issued: 06/02/2009
• Est. Priority Date: 07/07/2005
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Polhemus, Gary D., Jasa, Hrvoje, Snowdon, Kenneth P.
• Primary Examiner(s): Payne; David C
• Assistant Examiner(s): KASSA, ZEWDU A
• Application Number:
  US11/176,444
• Publication Number:
  US 20070009072A1
• Time in Patent Office: 1,426 Days
• Field of Search: 375/354, 375/316, 375/295, 375/219, 327/165, 327/166, 327/176, 370/395.62, 398/155, 714/20
• US Class Current: 375/354
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H04L 7/0037 Delay of clock signal
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/027 extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
• CPC Class Codes: H04L 7/0276 Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

Embodiments of the invention include an apparatus and method for continuously calibrating the frequency of a clock and data recovery (CDR) circuit. The apparatus includes a delay arrangement that generates a gating signal, and a gated voltage-controlled oscillator that is enabled by the gating signal. The gated voltage-controlled oscillator generates a recovered clock signal that is based on the data signal input to the CDR circuit. The apparatus also includes a frequency control loop that continuously calibrates the gated voltage-controlled oscillator in such a way that the frequency of the clock signal generated by the gated voltage-controlled oscillator continues to be one half of the period of the data bits in the input data signal and the clock signal remains synchronized to the center of the data state transitions of the input data signal. Alternatively, a secondary frequency control loop adjusts the amount of delay in the frequency control loop.

Claims

1. An integrated circuit including a clock and data recovery (CDR) circuit, the CDR circuit generating a clock signal based on an input data signal having a period 2τ

and including a plurality of data state transitions, the CDR circuit comprising;

a first delay arrangement for generating a gating signal of duration τ

based on the data state transitions of the input data signal, wherein the first delay arrangement includes a first delay element;

a gated voltage-controlled oscillator coupled to the first delay arrangement in such a way that the gating signal enables the gated voltage-controlled oscillator, wherein the gated voltage-controlled oscillator, when enabled, generates the clock signal, wherein the generated clock signal has a duration τ and

is synchronized to the center of the data state transitions of the input data signal,

wherein the gated voltage-controlled oscillator includes a first frequency control loop that continually calibrates the frequency of the gated voltage-controlled oscillator to generate the clock signal with the duration τ

, and delays the generated clock signal in such a way that the generated clock signal is synchronized to the center of the data state transitions of the input data signal; and

a secondary loop coupled to the first frequency control loop of the gated voltage-controlled oscillator and coupled to the first delay element of the first delay arrangement, wherein the secondary loop includes a frequency detector that tunes the first delay element and tunes the first frequency control loop of the gated voltage-controlled oscillator based on the frequency difference between a recovered clock signal output from the gated voltage-controlled oscillator and an output frequency of a phase locked loop coupled to the frequency detector.

2. The integrated circuit as recited in claim 1, wherein the gated voltage-controlled oscillator comprises a NAND/AND gate having a first gating input A, a second input B, a non-inverting output Y and an inverting output Y_b, wherein the gated voltage-controlled oscillator is coupled to the first delay arrangement in such a way that the gating signals generated by the first delay arrangement are received by the first gating input A, and wherein the non-inverting output Y generates the clock signal for the gated voltage-controlled oscillator.

3. The integrated circuit as recited in claim 2, wherein the frequency control loop comprises a second delay element coupled between the inverting output Y_b of the NAND/AND gate and the second input B of the NAND/AND gate.

4. The integrated circuit as recited in claim 3, wherein the clock and data recovery circuit further comprises a secondary frequency control loop coupled to the gated voltage-controlled oscillator for adjusting the amount of signal delay in the frequency control loop.

5. The integrated circuit as recited in claim 4, wherein the secondary frequency control loop adjusts the amount of signal delay in the first delay arrangement.

6. The integrated circuit as recited in claim 1, wherein the first delay arrangement comprises a XNOR gate having a first input that receives the input data signal, a second input that is coupled to the first delay element in such a way that the second input of the XNOR gate receives a version of the input data signal that has been delayed by the first delay element, and an output that generates the gating signal, wherein the gating signal has pulses of duration τ

that correspond to data state transitions of the input data signal.

7. The integrated circuit as recited in claim 1, further comprising a data extraction device, wherein the data extraction device has a first input D that receives the input data signal, a second input CLK that receives the generated clock signal, and an output Q that outputs the input data signal based on the generated clock signal received at the second input CLK, wherein the data extraction device synchronizes the input data signal output from the output Q with the generated clock signal received at the second input CLK.

8. The integrated circuit as recited in claim 7, wherein the data extraction device further comprises a master/slave data D flip-flop.

9. The integrated circuit as recited in claim 1, wherein the clock signal generated by the gated voltage-controlled oscillator has an average frequency, and wherein the clock and data recovery circuit further comprises a secondary frequency control loop coupled to the gated voltage-controlled oscillator for calibrating the gated voltage-controlled oscillator.

10. The integrated circuit as recited in claim 9, wherein the secondary frequency control loop generates a reference signal having a reference frequency, wherein the secondary frequency control loop further comprises a frequency detector for comparing the frequency of the reference signal to the average frequency of the clock signal generated by the gated voltage-controlled oscillator, and wherein the secondary frequency control loop calibrates the gated voltage-controlled oscillator based on the comparison of the frequency of the reference signal to the average frequency of the clock signal generated by the gated voltage-controlled oscillator.

11. The integrated circuit as recited in claim 9, wherein the secondary frequency control loop further comprises a phase-locked loop to generate the reference signal.

12. A method for recovering a clock signal from a data signal, wherein the data signal has a period 2τ

and includes a plurality of data state transitions, the method comprising the steps of;

providing the data signal;

providing a delay arrangement that delays a version of the data signal and uses the data signal and the delayed version of the data signal to generate a gating signal of duration τ

that corresponds to data state transitions of the data signal;

providing a gated voltage-controlled oscillator that is enabled by the gating signal, wherein the gated voltage-controlled oscillator, when enabled, generates the clock signal, wherein the generated clock signal has a duration τ and

is synchronized to the center of the data state transitions of the data signal;

calibrating the frequency of the gated voltage-controlled oscillator with a first frequency control loop in such a way the clock signal generated by the gated voltage-controlled oscillator has a duration τ and

is delayed in such a way that the clock signal remains synchronized to the center of the data state transitions of the data signal; and

tuning the delay arrangement and the first frequency control loop with a secondary loop coupled between the gated voltage-controlled oscillator and the delay arrangement, wherein the secondary loop includes a frequency detector that tunes the first delay arrangement and tunes the first frequency control loop of the gated voltage-controlled oscillator based on the frequency difference between a recovered clock signal output from the gated voltage-controlled oscillator and an output frequency of a phase locked loop coupled to the frequency detector.

13. The integrated circuit as recited in claim 12, further comprising the step of adjusting with a second frequency control loop the amount of signal delay in the first frequency control loop.

14. The integrated circuit as recited in claim 13, wherein the gated voltage-controlled oscillator has an average frequency, and wherein the adjusting step adjusts the amount of signal delay in the first frequency control loop based on a comparison of the average frequency of the gated voltage-controlled oscillator with a reference frequency.

15. The integrated circuit as recited in claim 12, further comprising the step of synchronizing the clock signal with the data signal with a data extraction device.

16. The integrated circuit as recited in claim 12, wherein the delay arrangement providing step further comprises the step of applying a logical XNOR operation to the data signal and the delayed version of the data signal to generate the gating signal.

17. An information transmission system, comprising:

a transmitter for generating a data signal, the data signal having a period 2τ and

including a plurality of data state transitions;

a transmission medium having a first end coupled to the transmitter and a second end, the transmission medium transmitting the data signal from the transmitter; and

a receiver coupled to the second end of the transmission medium for receiving the data signal generated by the transmitter and transmitted by the transmission medium, the receiver including an integrated circuit having a clock and data recovery circuit, the clock and data recovery circuit generating a recovered clock signal based on the data signal, the clock and data recovery circuit comprising

a first delay arrangement for generating a gating signal that has pulses of duration τ

that correspond to data state transitions of the data signal, wherein the first delay arrangement includes a first delay element,

a gated voltage-controlled oscillator coupled to the first delay arrangement in such a way that the gating signal enables the gated voltage-controlled oscillator, wherein the gated voltage-controlled oscillator, when enabled, generates the clock signal, wherein the generated clock signal has a duration τ and

is synchronized to the center of the data state transitions of the input data signal,

wherein the gated voltage-controlled oscillator includes a first frequency control loop that continually calibrates the frequency of the gated voltage-controlled oscillator to generate the clock signal with the duration τ

, the frequency control loop including a second delay element that delays the generated clock signal by τ

in such a way that the generated clock signal is synchronized to the center of the data state transitions of the input data signal, and

a secondary loop coupled to the first frequency control loop of the gated voltage-controlled oscillator and coupled to the first delay element of the first delay arrangement, wherein the secondary loop includes a frequency detector that tunes the first delay element in such a way that the gating signal causes the generated clock signal from the gated voltage-controlled oscillator to remain in the center of the data state transitions of the input data signal and tunes the first frequency control loop of the gated voltage-controlled oscillator in such a way that the frequency of the gated voltage-controlled oscillator matches the frequency of a phase locked loop coupled to the frequency detector, wherein the secondary loop tunes the first delay element and tunes the first frequency control loon of the gated voltage-controlled oscillator based on the frequency difference between a recovered clock signal output from the gated voltage-controlled oscillator and an output frequency of a phase locked loop coupled to the frequency detector.

18. The integrated circuit as recited in claim 17, wherein the clock signal generated by the gated voltage-controlled oscillator has an average frequency, and wherein the CDR circuit further comprises a secondary frequency control loop coupled to the gated voltage-controlled oscillator for adjusting the amount of signal delay by the second delay element based on a comparison of the average frequency of the clock signal generated by the gated voltage-controlled oscillator with a reference frequency.

19. The integrated circuit as recited in claim 18, wherein the secondary frequency control loop generates the reference frequency, and wherein the secondary frequency control loop further comprises a frequency detector for comparing the reference frequency to the average frequency of the clock signal generated by the gated voltage-controlled oscillator.

20. The integrated circuit as recited in claim 18, wherein the secondary frequency control loop further comprises a phase-locked loop to generate the reference frequency.

21. The integrated circuit as recited in claim 17, further comprising a data extraction device coupled to the gated voltage-controlled oscillator that synchronizes the data signal with the clock signal generated from the gated voltage-controlled oscillator.