Safe message transfers on PCI-Express link from RAID controller to receiver-programmable window of partner RAID controller CPU memory
First Claim
1. A fault-tolerant mass storage system, comprising:
- first and second RAID controllers, coupled for communication via a PCI-Express link, each comprising;
a bus bridge, coupled to said link and to first and second buses;
a cache memory, coupled to said first bus, configured to cache user data for storage on disk drives controlled by said controllers; and
a CPU, and a CPU memory coupled to said CPU, each coupled to said second bus, wherein said CPU is configured to fetch and execute program instructions from said CPU memory, wherein said CPU is configured to program said bus bridge with window information defining a window of locations within said CPU memory, wherein said window comprises less than an entirety of said CPU memory;
wherein said bus bridge is configured to receive data on said link from the other of said first and second RAID controllers, to write said data to said CPU memory if destined for said CPU memory, but only within said window and nowhere else within said CPU memory, and to write said data to said cache memory if destined for said cache memory, wherein said bus bridge is configured to refrain from writing said data to said CPU memory outside of said window even if said bus bridge determines that a portion of said data is destined for said CPU memory within said window.
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Accused Products
Abstract
A fault-tolerant mass storage system includes two RAID controllers that communicate via a PCI-Express link. Each controller has a bus bridge coupled to the link, a cache memory that caches user data for storage on disk drives controlled by the controllers, and a CPU. The CPU fetches and executes program instructions from a CPU memory coupled to it. The CPU programs the bus bridge with window information defining a window of locations within the CPU memory, which is less than an entirety of the CPU memory. The bus bridge receives data on the link from the other controller and if the header of a packet containing the data indicates it is destined for the CPU memory, the bus bridge translates the address of the data so as to write the data safely to the CPU memory, but only within the window and nowhere else within the CPU memory.
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Citations
64 Claims
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1. A fault-tolerant mass storage system, comprising:
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first and second RAID controllers, coupled for communication via a PCI-Express link, each comprising; a bus bridge, coupled to said link and to first and second buses; a cache memory, coupled to said first bus, configured to cache user data for storage on disk drives controlled by said controllers; and a CPU, and a CPU memory coupled to said CPU, each coupled to said second bus, wherein said CPU is configured to fetch and execute program instructions from said CPU memory, wherein said CPU is configured to program said bus bridge with window information defining a window of locations within said CPU memory, wherein said window comprises less than an entirety of said CPU memory; wherein said bus bridge is configured to receive data on said link from the other of said first and second RAID controllers, to write said data to said CPU memory if destined for said CPU memory, but only within said window and nowhere else within said CPU memory, and to write said data to said cache memory if destined for said cache memory, wherein said bus bridge is configured to refrain from writing said data to said CPU memory outside of said window even if said bus bridge determines that a portion of said data is destined for said CPU memory within said window. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A method for reliably transferring data between first and second RAID controllers via a PCI-Express link in a fault-tolerant mass storage system, the first RAID controller having a first bus bridge coupled to the link, to a first cache memory for caching user data for storage on disk drives controlled by the first RAID controller, to a first CPU, and to a first CPU memory for storing program instructions fetched and executed by the first CPU, the second RAID controller having a second bus bridge coupled to the link, to a second cache memory for caching user data for storage on disk drives controlled by the second RAID controller, to a second CPU, and to a second CPU memory for storing program instructions fetched and executed by the second CPU, the method comprising:
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programming, by the first CPU, the first bus bridge with window information defining a window of locations within the first CPU memory, wherein the window comprises less than an entirety of the first CPU memory; receiving, by the first bus bridge, data on the link from the second bus bridge; writing, by the first bus bridge, the data to the first CPU memory if the data is destined for the first CPU memory, but only within the window and nowhere else within the first CPU memory; refraining, by the first bus bridge, from writing the data to the first CPU memory outside of the window even if the first bus bridge determines that a portion of the data is destined for the first CPU memory within the window; and writing, by the first bus bridge, the data to the first cache memory if the data is destined for the first cache memory. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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40. A bus bridge, for instantiation on each of two redundant array of inexpensive disks (RAID) controllers coupled for communication on a PCI-Express link, the bus bridge comprising:
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a PCI-Express interface, for coupling to said link, wherein said PCI-Express interface is configured to receive data on said link from said PCI-Express interface of the other RAID controller; a memory bus interface, for coupling to a cache memory, configured to cache user data for storage on disk drives controlled by said controllers; a local bus interface, for coupling to a CPU and to a CPU memory from which said CPU fetches and executes program instructions; at least one control register, programmable by said CPU with window information defining a window of locations within said CPU memory, said window comprising less than an entirety of said CPU memory; and control logic, coupled to said interfaces, wherein said control logic is configured to determine whether said received data is destined for said CPU memory, and if so, to control said local bus interface to write said data to said CPU memory, but only within said window and nowhere else within said CPU memory, and to determine whether said data is destined for said cache memory, and if so, to control the memory bus interface to write said data to said cache memory, wherein said control logic is configured to refrain from controlling said memory bus interface to write said data to said CPU memory outside of said window even if said control logic determines that a portion of said data is destined for said CPU memory within said window. - View Dependent Claims (41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60)
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61. A fault-tolerant mass storage system, comprising:
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first and second RAID controllers, coupled for communication via a PCI-Express link, each comprising; a bus bridge, coupled to said link; a CPU memory, coupled to said bus bridge, configured to store program instructions and to cache user data for storage on disk drives controlled by said controllers; and a CPU, coupled to said CPU memory and to said bus bridge, configured to fetch and execute said program instructions from said CPU memory, to control caching of said user data in said CPU memory, and to program said bus bridge with window information defining a window of locations within said CPU memory, wherein said window comprises less than an entirety of said CPU memory; wherein said bus bridge is configured to receive data on said link from the other of said first and second RAID controllers, and to write said data to said CPU memory, but only within said window and nowhere else within said CPU memory, wherein said bus bridge is configured to refrain from writing said data to said CPU memory outside of said window even if said bus bridge determines that a portion of said data is destined for said CPU memory within said window.
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62. A method for reliably transferring data between first and second RAID controllers via a PCI-Express link in a fault-tolerant mass storage system, each of the RAID controllers having a bus bridge coupled to the link, to a CPU, and to a CPU memory for storing program instructions fetched and executed by the CPU and for caching user data for storage on disk drives controlled by the RAID controllers, the method comprising:
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programming, by the first CPU, the first bus bridge with window information defining a window of locations within the first CPU memory, wherein the window comprises less than an entirety of the CPU memory; receiving, by the first bus bridge, data on the link from the second bus bridge; writing, by the first bus bridge, the data to the first CPU memory, but only within the window and nowhere else within the first CPU memory; and refraining, by the first bus bridge, from writing the data to the first CPU memory outside of the window even if the first bus bridge determines that a portion of the data is destined for the first CPU memory within the window.
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63. A bus bridge, for instantiation on each of two redundant array of inexpensive disks (RAID) controllers coupled for communication on a PCI-Express link, the bus bridge comprising:
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a PCI-Express interface, for coupling to said link, wherein said PCI-Express interface is configured to receive data on said link from said PCI-Express interface of the other RAID controller; a local bus interface, for coupling to a CPU and to a CPU memory from which said CPU fetches and executes program instructions and which caches user data for storage on disk drives controlled by the controllers; at least one control register, programmable by said CPU with window information defining a window of locations within said CPU memory, said window comprising less than an entirety of said CPU memory; and control logic, coupled to said interfaces, wherein said control logic is configured to control said local bus interface to write said data to said CPU memory, but only within said window and nowhere else within said CPU memory, wherein said control logic is configured to refrain from controlling said local bus interface to write said data to said CPU memory outside of said window even if said control logic determines that a portion of said data is destined for said CPU memory within said window.
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64. A bus bridge, for instantiation on each of two redundant array of inexpensive disks (RAID) controllers coupled for communication on a PCI-Express link, the bus bridge comprising:
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a PCI-Express interface, for coupling to said link, wherein said PCI-Express interface is configured to receive data on said link from said PCI-Express interface of the other RAID controller; a first bus interface, for coupling to a CPU; a second bus interface, for coupling to a CPU memory from which said CPU fetches and executes program instructions and which caches user data for storage on disk drives controlled by the controllers; at least one control register, programmable by said CPU with window information defining a window of locations within said CPU memory, said window comprising less than an entirety of said CPU memory; and control logic, coupled to said interfaces, wherein said control logic is configured to control said second bus interface to write said data to said CPU memory, but only within said window and nowhere else within said CPU memory, wherein said control logic is configured to refrain from controlling said second bus interface to write said data to said CPU memory outside of said window even if said control logic determines that a portion of said data is destined for said CPU memory within said window.
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Specification