Low power method of monitoring and of responsively initiating higher powered intelligent response to detected change of condition

• US 7,543,163 B2
• Filed: 01/04/2006
• Issued: 06/02/2009
• Est. Priority Date: 01/05/2005
• Status: Expired due to Fees

• Current Assignee: Exar Corporation (Maxlinear Incorporated)
• Original Assignee: Exar Corporation (Maxlinear Incorporated)
• Inventors: Kernahan, Kent, Lambert, Craig Norman, Thomas, John Carl
• Primary Examiner(s): CONNOLLY, MARK A
• Application Number:
  US11/326,104
• Publication Number:
  US 20060176040A1
• Time in Patent Office: 1,245 Days
• Field of Search: 713/300, 713/320, 713/322, 713/340
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A synchronous control system includes a logic controller (e.g., microprocessor) which can be put into low power standby or sleep mode by shutting off its clock. A quick-start oscillator (QSO) remains shut off to conserve power when not needed, but awakens rapidly and supplies clock signals to the logic controller for quickly awakening the controller so the latter can to respond to exigent circumstances. One such circumstance can be the drop of a vital supply voltage below a predefined threshold. A low power comparator (LPTC) detects the drop and starts up the QSO which in turn awakens the controller. The controller determines what the reason for the awakening is, quickly responds to the exigent circumstance and then turns the QSO off to thereby conserve power and put itself (QSO) back to sleep. Disclosures are provided for the QSO and a first calibration subsystem used to maintain QSO output frequency within a desired range. Disclosures are provided for the LPTC and a second calibration subsystem used to set its trigger threshold. Disclosure of a novel DAC within the LPTC is also provided.

Claims

1. A method of monitoring one or more conditions of a system that is temporarily in a relatively low-powered mode as compared to a more normal, higher powered mode where the monitoring is to be followed by intelligent response to one or more detected changes of one or more of the monitored conditions, the method comprising:

(a) using a set of one or more, low-powered analog to monitor said one or more conditions for respectively detecting changes of condition that are predefined as alert-worthy changes, wherein one or more of said alert-worthy changes of condition are detected by comparing a respectively monitored analog signal relative to a correspondingly supplied reference signal while said system is in its more normal, higher powered mode rather than the relatively low-powered mode, adjusting at least one of said reference signals as respectively supplied to one or more given ones of the low-powered analog comparators, where said adjusting counter-compensates for one or more errors in signaling pathways of each respective one of the given low-powered analog comparators where said counter-compensated-for errors include at least one of a comparator offset error and a DAC offset error;

(b) in response to one of said analog comparators detecting an alert-worthy change of condition, quickly starting up an oscillator within one millisecond or less of said detecting of the alert-worthy change of condition; and

(c) using the quickly started up oscillator to clock a first logical responding unit and to thereby enable the first logical responding unit to respond to the detecting of an alert-worthy change of condition by one or more of said low-powered analog comparators.

2. The method of claim 1 wherein:

(a.1) one or more of said alert-worthy changes of condition is defined as a unidirectional crossing of the respectively monitored condition either above or below a predefined threshold.

3. The method of claim 2 and further comprising:

(a.2) programmably defining said predefined threshold prior to commencement of said monitoring and while said system is not in its relatively low-powered mode.

4. The method of claim 1 wherein:

(a.1) one or more of said alert-worthy changes of condition is defined as a departure of the monitored condition from a predefined containment range.

5. The method of claim 4 and further comprising:

(a.2) programmably defining said predefined containment range prior to commencement of said monitoring and while said system is not in its relatively low-powered mode.

6. The method of claim 1 and further comprising:

(d) reducing power draw of the first logical responding unit prior to commencement of said low power monitoring by stopping supply of clock signals to the first logical responding unit while leaving the first logical responding unit in a state where it will be awakened immediately or within a few number of start up ticks of the quick start oscillator following start up of said quick start oscillator, where said few number is less than or equal to 100.

7. The method of claim 6 wherein said few number is 8 or less.

8. The method of claim 6 wherein said few number is in the range 2 to 100 inclusive.

9. The method of claim 6 wherein said system includes one or more further logical units in addition to said first logical responding unit and said method includes:

(e) reducing power draw of the one or more further logical units prior to commencement of said low power monitoring by stopping supply of clock signals to said further logical units while leaving the one or more further logical responding units in respective states where they can be awakened by start of their respectively stopped clock signals; and

(f) keeping the one or more further logical units in their respective unclocked, asleep states while the first logical responding unit awakens to respond to the detecting of an alert-worthy change of condition by one or more of said low-powered analog comparators.

10. The method of claim 1 and further comprising:

(c.1) upon using the started up oscillator to clock the first logical responding unit, further causing the first logical responding unit to determine which, if any, low-powered analog comparator signaled the alert-worthy change of condition that led to the start up of said oscillator.

11. The method of claim 1 wherein the quickly started oscillator is a variable frequency oscillator, and the method further comprises:

(b.1) comparing the output frequency of the started variable frequency oscillator to a predefined target value, and if the frequency comparison indicates an off target condition, adjusting the output frequency of the started variable frequency oscillator towards convergence with the target value.

12. The method of claim 11 wherein the target value represents a frequency which is at least 10 times greater than a reference frequency of a supplied reference clock signal and the target value is programmably set.

13. The method of claim 11 and further comprising:

(b.2) recording data representing the state of the variable frequency oscillator after said adjusting of the output frequency so that the variable frequency oscillator can be restarted in a state defined by the recorded data when restarting in response to one of said analog comparators detecting a next alert-worthy change of condition.

14. The method of claim 1 wherein the quickly started oscillator is a variable frequency oscillator, and the method further comprises:

(c.1) preventing the quickly started up oscillator from clocking the first logical responding unit until the quickly started up oscillator has a frequency below a predefined maximum frequency.

15. The method of claim 14 and further comprising:

(c.2) starting the quickly started up oscillator in a state where the output frequency of the started up oscillator can be greater than said predefined maximum frequency.

16. A system having a relatively low-powered, sleep mode and one or more system vital conditions that may require monitoring during the sleep mode to assure that the system can be awakened without loss of operational states developed prior to entry into the low-powered, said system also having a higher powered mode and comprising:

(a) one or more, low-powered analog comparators coupled to monitor said one or more system vital conditions for respectively pre-defined, alert-worthy changes of condition, wherein at least a given one of said low-powered analog comparators is coupled to receive a respective monitored analog signal and a corresponding reference signal against which the respective monitored analog signal is to be compared within the given analog comparator, and further comprising a digital-to-analog converter (DAC) operatively coupled to produce said corresponding reference signal, a DAC-controlling memory operatively coupled to supply a digital input word to said DAC for thereby producing the corresponding reference signal, and an analog-to-digital converter (ADC) operatively coupled to said given analog comparator for measuring an output of the given analog comparator when a given digital input word is supplied to said DAC for thereby producing the corresponding reference signal;

(b) one or more quick-start oscillators, each operatively coupled to one or more of said analog comparators for quickly starting up within one millisecond or less in response to a detecting of an alert-worthy change of condition by a corresponding one of said analog comparators; and

(c) a first logic unit that can be started up out of a respective first low power state by activation of at least one of said quick-start oscillators, the clocking of the first logic unit enabling the first logic unit to respond to the detecting of an alert-worthy change of condition by one or more of said low-powered analog comparators.

17. The system of claim 16 and further comprising:

(a.5) input shorting means operatively coupled to the given analog comparator for temporarily shorting the ADC-measured output of the given analog comparator to an input thereof so that the given analog comparator behaves substantially as a unity gain amplifier.

18. The system of claim 16 and further comprising:

(a.5) a multiplexer operatively coupled to the analog-to-digital converter (ADC) so that the ADC can be used to measure a supply voltage and relay the measurement data to the first logic unit.

19. The system of claim 18 wherein the ADC is operatively coupled to receive a clock signal output by at least one of the awakened quick-start oscillators.

20. The system of claim 16 wherein:

(a.1) at least a given one of said low-powered analog comparators is configured to more strongly react to a first unidirectional crossing of a respectively monitored condition past a predefined threshold than to react to an opposed second unidirectional crossing of the respectively monitored condition past the predefined threshold thereby causing the first unidirectional crossing to function as an alert-worthy change of condition.

21. The system of claim 16 and further comprising:

(d) power down means for placing one or more of the low-powered analog comparators in respective power down modes.

22. The system of claim 16 and further comprising:

(d) a second logic unit that is not awakened out of a respective second low power state by activation of at least one of said quick-start oscillators that starts up the first logic unit out of its respective first low power state.

23. The system of claim 16 and further comprising:

(d) alert source identifying logic, operatively coupled to the first logic unit for allowing the first logic unit to determine which, if any, of the low-powered analog comparators signaled an alert-worthy change of condition that led to the start up of at least one of said quick-start oscillators and consequential start up of the first logic unit.

24. The system of claim 16 wherein at least a given one quickly started oscillator (QSO) includes a variable frequency oscillator, and the given QSO further comprises:

(b.1) a frequency calibrator structured to compare the output frequency of the variable frequency oscillator to a predefined target value, and if the frequency comparison indicates an off target condition, to adjust the output frequency of the variable frequency oscillator towards convergence with the target value.

25. The system of claim 24 wherein the given QSO further comprises:

(b.2) adjustment memory for storing data representing a frequency adjustment earlier made by the frequency calibrator, the adjustment memory being operatively coupled to the variable frequency oscillator such that when the given QSO is restarted or is further calibrated, results of the earlier made frequency adjustment can be used for making a next frequency adjustment.

26. The system of claim 24 and further comprising:

(d) a low frequency reference clock operatively coupled to the frequency calibrator of the given QSO for allowing the frequency calibrator to compare the output frequency of the variable frequency oscillator against a reference frequency of a reference clock signal produced by the low frequency reference clock, wherein the target value represents a frequency which is at least 10 times greater than said reference frequency of the low frequency reference clock.

27. The system of claim 26 and further comprising:

(e) target storage for storing the target value as a programmably set data signal.

28. The system of claim 27 and further comprising:

(f) preset storage for storing preset data representing an initial state of the variable frequency oscillator from which the variable frequency oscillator is to be calibrated to attain a target frequency represented by the target value.

29. The system of claim 16 and further comprising:

(a.1) one or more programmable storage units for programmably defining said alert-worthy changes of condition to be detected by respective ones of said low-powered analog comparators.

30. The system of claim 29 wherein:

(a.2) said one or more programmable storage units are operatively coupled to an error compensating means that adjusts the programmable definition of the alert-worthy change of condition to counter-compensate for an offset error and/or other error associated with one or both of the analog comparator which monitors the respectively monitored condition and a digital-to-analog converter (DAC) which converts into an analog counterpart, the programmable definition of the alert-worthy change of condition.