Low power method of monitoring and of responsively initiating higher powered intelligent response to detected change of condition
First Claim
1. A method of monitoring one or more conditions of a system that is temporarily in a relatively low-powered mode as compared to a more normal, higher powered mode where the monitoring is to be followed by intelligent response to one or more detected changes of one or more of the monitored conditions, the method comprising:
- (a) using a set of one or more, low-powered analog to monitor said one or more conditions for respectively detecting changes of condition that are predefined as alert-worthy changes, wherein one or more of said alert-worthy changes of condition are detected by comparing a respectively monitored analog signal relative to a correspondingly supplied reference signal while said system is in its more normal, higher powered mode rather than the relatively low-powered mode, adjusting at least one of said reference signals as respectively supplied to one or more given ones of the low-powered analog comparators, where said adjusting counter-compensates for one or more errors in signaling pathways of each respective one of the given low-powered analog comparators where said counter-compensated-for errors include at least one of a comparator offset error and a DAC offset error;
(b) in response to one of said analog comparators detecting an alert-worthy change of condition, quickly starting up an oscillator within one millisecond or less of said detecting of the alert-worthy change of condition; and
(c) using the quickly started up oscillator to clock a first logical responding unit and to thereby enable the first logical responding unit to respond to the detecting of an alert-worthy change of condition by one or more of said low-powered analog comparators.
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Accused Products
Abstract
A synchronous control system includes a logic controller (e.g., microprocessor) which can be put into low power standby or sleep mode by shutting off its clock. A quick-start oscillator (QSO) remains shut off to conserve power when not needed, but awakens rapidly and supplies clock signals to the logic controller for quickly awakening the controller so the latter can to respond to exigent circumstances. One such circumstance can be the drop of a vital supply voltage below a predefined threshold. A low power comparator (LPTC) detects the drop and starts up the QSO which in turn awakens the controller. The controller determines what the reason for the awakening is, quickly responds to the exigent circumstance and then turns the QSO off to thereby conserve power and put itself (QSO) back to sleep. Disclosures are provided for the QSO and a first calibration subsystem used to maintain QSO output frequency within a desired range. Disclosures are provided for the LPTC and a second calibration subsystem used to set its trigger threshold. Disclosure of a novel DAC within the LPTC is also provided.
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Citations
30 Claims
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1. A method of monitoring one or more conditions of a system that is temporarily in a relatively low-powered mode as compared to a more normal, higher powered mode where the monitoring is to be followed by intelligent response to one or more detected changes of one or more of the monitored conditions, the method comprising:
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(a) using a set of one or more, low-powered analog to monitor said one or more conditions for respectively detecting changes of condition that are predefined as alert-worthy changes, wherein one or more of said alert-worthy changes of condition are detected by comparing a respectively monitored analog signal relative to a correspondingly supplied reference signal while said system is in its more normal, higher powered mode rather than the relatively low-powered mode, adjusting at least one of said reference signals as respectively supplied to one or more given ones of the low-powered analog comparators, where said adjusting counter-compensates for one or more errors in signaling pathways of each respective one of the given low-powered analog comparators where said counter-compensated-for errors include at least one of a comparator offset error and a DAC offset error; (b) in response to one of said analog comparators detecting an alert-worthy change of condition, quickly starting up an oscillator within one millisecond or less of said detecting of the alert-worthy change of condition; and (c) using the quickly started up oscillator to clock a first logical responding unit and to thereby enable the first logical responding unit to respond to the detecting of an alert-worthy change of condition by one or more of said low-powered analog comparators. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A system having a relatively low-powered, sleep mode and one or more system vital conditions that may require monitoring during the sleep mode to assure that the system can be awakened without loss of operational states developed prior to entry into the low-powered, said system also having a higher powered mode and comprising:
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(a) one or more, low-powered analog comparators coupled to monitor said one or more system vital conditions for respectively pre-defined, alert-worthy changes of condition, wherein at least a given one of said low-powered analog comparators is coupled to receive a respective monitored analog signal and a corresponding reference signal against which the respective monitored analog signal is to be compared within the given analog comparator, and further comprising a digital-to-analog converter (DAC) operatively coupled to produce said corresponding reference signal, a DAC-controlling memory operatively coupled to supply a digital input word to said DAC for thereby producing the corresponding reference signal, and an analog-to-digital converter (ADC) operatively coupled to said given analog comparator for measuring an output of the given analog comparator when a given digital input word is supplied to said DAC for thereby producing the corresponding reference signal; (b) one or more quick-start oscillators, each operatively coupled to one or more of said analog comparators for quickly starting up within one millisecond or less in response to a detecting of an alert-worthy change of condition by a corresponding one of said analog comparators; and (c) a first logic unit that can be started up out of a respective first low power state by activation of at least one of said quick-start oscillators, the clocking of the first logic unit enabling the first logic unit to respond to the detecting of an alert-worthy change of condition by one or more of said low-powered analog comparators. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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Specification