Method and system for allowing code to be securely initialized in a computer
First Claim
1. One or more computer-readable media having stored thereon a plurality of instructions that, when executed by one or more processors of a computer, causes the one or more processors to perform acts including:
- booting, based on untrustworthy code, a computer;
loading a trusted core into memory; and
initiating secure execution of the trusted core by;
mapping a central processing unit reset vector to an initialization vector;
resetting each of one or more central processing units in the computer;
receiving, after the mapping and the resetting, a read request corresponding to the central processing unit reset vector from one of the one or more central processing units;
returning, in response to the read request, the initialization vector to the one central processing unit; and
allowing the one central processing unit to access the memory beginning with the initialization vector.
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Accused Products
Abstract
A memory controller prevents CPUs and other I/O bus masters from accessing memory during a code (for example, trusted core) initialization process. The memory controller resets CPUs in the computer and allows a CPU to begin accessing memory at a particular location (identified to the CPU by the memory controller). Once an initialization process has been executed by that CPU, the code is operational and any other CPUs are allowed to access memory (after being reset), as are any other bus masters (subject to any controls imposed by the initiated code).
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Citations
14 Claims
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1. One or more computer-readable media having stored thereon a plurality of instructions that, when executed by one or more processors of a computer, causes the one or more processors to perform acts including:
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booting, based on untrustworthy code, a computer; loading a trusted core into memory; and initiating secure execution of the trusted core by; mapping a central processing unit reset vector to an initialization vector; resetting each of one or more central processing units in the computer; receiving, after the mapping and the resetting, a read request corresponding to the central processing unit reset vector from one of the one or more central processing units; returning, in response to the read request, the initialization vector to the one central processing unit; and allowing the one central processing unit to access the memory beginning with the initialization vector. - View Dependent Claims (2, 3, 4)
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5. A system comprising:
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means for booting, based on untrustworthy code, a computer; means for loading a trusted core into memory; and means for initiating secure execution of the trusted core including; means for mapping a central processing unit reset vector to an initialization vector; means for resetting each of one or more central processing units in the computer; means for receiving, after the mapping and the resetting, a read request corresponding to the central processing unit reset vector from one of the one or more central processing units; means for returning, in response to the read request, the initialization vector to the one central processing unit; and means for allowing the one central processing unit to access the memory beginning with the initialization vector. - View Dependent Claims (6, 7, 8)
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9. One or more computer-readable media having stored thereon a plurality of instructions that, when executed by one or more processors of a computer, causes the one or more processors to perform acts including:
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allowing a computer to begin operation based on untrustworthy code; loading, under the control of the untrustworthy code, additional code into memory; initiating execution of the additional code in a secure manner despite the untrustworthy code in the computer; mapping a central processing unit reset vector to an initialization vector; receiving a read request corresponding to the central processing unit reset vector from one central processing unit; returning, in response to the read request, the initialization vector to the one central processing unit; and allowing the one central processing unit to access the memory beginning with the initialization vector. - View Dependent Claims (10, 11, 12, 13, 14)
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Specification