Fabrication method of semiconductor integrated circuit device

• US 7,544,522 B2
• Filed: 06/09/2004
• Issued: 06/09/2009
• Est. Priority Date: 06/09/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Hirota, Daisuke, Watanabe, Koji, Kanda, Makoto
• Primary Examiner(s): Smoot; Stephen W
• Application Number:
  US11/628,776
• Publication Number:
  US 20070231936A1
• Time in Patent Office: 1,826 Days
• Field of Search: 438/15
• US Class Current: 438/16
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0392 specifically adapted to include a probing step
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05085 with additional elements, e.g. vias arrays, interposed between the stacked layers
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides

Abstract

To prevent breakage of a membrane probe during a probe test using a probe card having the membrane probe, appearance of a main surface of a wafer as a test object is tested by an appearance tester 51, and results of bad appearance such as adhesion of a foreign substance to the main surface of the wafer and abnormality in shape of bump electrodes over the main surface of the wafer are collected as wafer map data according to arrangement of respective chips in a plane of the wafer, then the wafer map data are transmitted to a probe tester 53 via a server 52, and the probe tester 53 omits the probe test for chips in which bad appearance was detected, and concurrently performs the probe test to other chips in which bad appearance was not detected, based on the wafer map data.

Claims

1. A fabrication method of a semiconductor integrated circuit device comprising the steps of:

(a) preparing a wafer in which a wafer process is substantially completed, and bonding pad openings or bump electrodes over bonding pads are formed in a plurality of chip regions respectively in a process of fabricating a semiconductor integrated circuit;

(b) performing an appearance test for at least the bonding pad openings or the bump electrodes and peripheries of them in each of the chip regions over the wafer; and

(c) performing the probe test for a second group of chip regions that do not belong to the first group using the membrane probe, without performing the probe test for a first group of one or more chip regions, which are inappropriate to be subjected to the probe test using the membrane probe, among the chip regions, based on a result of the appearance test when the chip regions are subjected to a probe test using a membrane probe,

wherein the appearance test of the step (b) comprises the following subordinate steps of;

(1) performing the appearance test to the bonding pad openings or the bump electrodes and peripheries of them at a first accuracy; and

(2) performing the appearance test to portions other than the bonding pad openings or the bump electrodes and the peripheries of them at a second accuracy rougher than said first accuracy.

2. The fabrication method of the semiconductor integrated circuit device according to claim 1:

wherein projection needles of the membrane probe are not contacted to the bonding pads or the bump electrodes as electrodes for probes for the first group of chip regions during the probe test of the step (c).

3. The fabrication method of the semiconductor integrated circuit device according to claim 2:

wherein the electrodes for probes are bump electrodes.

4. The fabrication method of the semiconductor integrated circuit device according to claim 3:

wherein the electrodes for probes are bump electrodes containing gold as a major component.

5. The fabrication method of the semiconductor integrated circuit device according to claim 2:

wherein the electrodes for probes are bonding pads.

6. The fabrication method of the semiconductor integrated circuit device according to claim 2:

wherein the electrodes for probes are bonding pads containing aluminum as a major component.

7. The fabrication method of the semiconductor integrated circuit device according to claim 1:

wherein the projection needles of the membrane probe are not contacted to the bonding pads or the bump electrodes as electrodes for probes to a level at which at least electrical measurement can be performed for the first group of chip regions during the probe test of the step (c).

8. The fabrication method of the semiconductor integrated circuit device according to claim 1:

the appearance test of the step (b) includes a step of optically testing whether a foreign substance or an abnormal pattern on the wafer damages the membrane probe during the probe test of the step (c).

9. The fabrication method of the semiconductor integrated circuit device according to claim 1:

wherein at least part of an interconnection layer below the bonding pads or the bump electrodes includes a buried wiring line formed of a wiring material containing copper as a major component.

10. A fabrication method of a semiconductor integrated circuit device, comprising the steps of:

(a) preparing a wafer in which a wafer process is substantially completed, and electrodes for probes are formed in a plurality of chip regions respectively, in a fabrication process of a semiconductor integrated circuit;

(b) performing an appearance test for at least the electrodes for probes and peripheries of them in each of the chip regions over the wafer; and

(c) performing the probe test for a second group of chip regions that do not belong to the first group using the membrane probe, without performing the probe test for a first group of one or more chip regions, which are inappropriate to be subjected to the probe test using the membrane probe, and contacting projection needles of the membrane probe to the electrodes for probes, among the chip regions, based on a result of the appearance test when the chip regions are subjected to a probe test using a membrane probe,

wherein the appearance test of the step (b) comprises the following subordinate steps of;

(1) performing the appearance test to the electrodes for probes and peripheries of them at a first accuracy; and

(2) performing the appearance test to portions other than the electrodes for probes and the peripheries of them at a second accuracy rougher than the first accuracy.

11. The fabrication method of the semiconductor integrated circuit device according to claim 10:

wherein the appearance test of the step (b) includes optically testing whether a foreign substance or an abnormal pattern over the wafer damages the membrane probe during the probe test of the step (c).

12. The fabrication method of the semiconductor integrated circuit device according to claim 10:

wherein the electrodes for probes are bump electrodes.

13. The fabrication method of the semiconductor integrated circuit device according to claim 10:

wherein the electrodes for probes are bonding pads.

14. The fabrication method of the semiconductor integrated circuit device according to claim 10:

wherein the electrodes for probes are bump electrodes containing gold as a major component.

15. The fabrication method of the semiconductor integrated circuit device according to claim 10:

wherein the electrodes for probes are bonding pads containing aluminum as a major component.

16. The fabrication method of the semiconductor integrated circuit device according to claim 10:

wherein at least part of an interconnection layer below the electrodes for probes includes a buried wiring line formed of a wiring material containing copper as a major component.

17. A fabrication method of a semiconductor integrated circuit device, comprising the steps of:

(a) preparing a wafer in which a wafer process is substantially completed, and gold bump electrodes containing gold as a major component are formed in a plurality of chip regions respectively, in a process of fabricating a semiconductor integrated circuit;

(b) performing an appearance test for at least the gold bump electrodes and peripheries of them in each of the chip regions over the wafer; and

(c) performing the probe test for a second group of chip regions that do not belong to the first group using the membrane probe, without performing the probe test for a first group of one or more chip regions, which are inappropriate to be subjected to the probe test using the membrane probe, and contacting projection needles of the membrane probe to the gold bump electrodes to a level at which at least electrical measurement can be performed, among the chip regions, based on a result of the appearance test when the chip regions are subjected to a probe test using a membrane probe,

wherein the appearance test of the step (b) comprises the following subordinate steps of;

(1) performing the appearance test to the gold bump electrodes and peripheries of them at a first accuracy; and

(2) performing the appearance test to portions other than the gold bump electrodes and the peripheries of them at a second accuracy rougher than the first accuracy.