Method of creating isolated electrodes in a nanowire-based device

• US 7,544,591 B2
• Filed: 01/18/2007
• Issued: 06/09/2009
• Est. Priority Date: 01/18/2007
• Status: Active Grant

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Sharma, Shashank, Kamins, Theodore I
• Primary Examiner(s): Dang; Phuc T
• Application Number:
  US11/624,682
• Publication Number:
  US 20080173971A1
• Time in Patent Office: 873 Days
• Field of Search: 438/481, 438/482, 438/486, 438/488, 257/506, 257/627
• US Class Current: 438/486
• CPC Class Codes: B81C 1/00095 Interconnects
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02645 Seed materials
• CPC Class Codes: H01L 21/02647 Lateral overgrowth
• CPC Class Codes: H01L 21/02653 Vapour-liquid-solid growth
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2221/1094 Conducting structures comprising nanotubes or nanowires
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods of creating isolated electrodes and integrating a nanowire therebetween each employ lateral epitaxial overgrowth of a semiconductor material on a semiconductor layer to form isolated electrodes having the same crystal orientation. The methods include selective epitaxial growth of a semiconductor feature through a window in an insulating film on the semiconductor layer. A vertical stem is in contact with the semiconductor layer through the window and a ledge is a lateral epitaxial overgrowth of the vertical stem on the insulating film. The methods further include creating a pair of isolated electrodes from the semiconductor feature and the semiconductor layer. A nanowire-based device includes the pair of isolated electrodes and a nanowire bridging between respective surfaces of the isolated electrodes of the pair.

Claims

1. A method of creating isolated electrodes in a nanowire-based device comprising:

providing a substrate that comprises a semiconductor layer having a crystal orientation and an insulating film on a surface of the semiconductor layer, the insulating film having a window to expose a portion of the surface;

selectively epitaxially growing a semiconductor feature from the surface through the window, the semiconductor feature having a vertical stem and a ledge that have the crystal orientation of the semiconductor layer, the vertical stem being in contact with the semiconductor layer through the window, the ledge being a lateral epitaxial overgrowth of the vertical stem on the insulating film; and

creating a pair of isolated electrodes from the semiconductor feature and the semiconductor layer.

2. The method of creating isolated electrodes of claim 1, wherein creating a pair of isolated electrodes comprises:

electrically isolating the ledge from the semiconductor layer;

creating a first electrode from the ledge; and

creating a second electrode from a region of the semiconductor layer that faces the ledge.

3. The method of creating isolated electrodes of claim 1, further comprising growing a nanowire vertically between the pair of isolated electrodes to self-assemble between the isolated electrodes of the pair, wherein growing a nanowire comprises:

providing a nanoparticle catalyst on a horizontal surface of one of the isolated electrodes of the pair; and

catalyzing nanowire growth vertically from the horizontal surface using the nanoparticle catalyst until a free end of the nanowire impinges on a facing horizontal surface of another of the electrodes of the pair.

4. The method of creating isolated electrodes of claim 1, wherein creating a pair of isolated electrodes comprises:

removing the insulating film to expose the semiconductor layer surrounding the semiconductor feature, the ledge extending from the vertical stem to cantilever over the semiconductor layer; and

isolating portions of the semiconductor feature from one another by implanting a species into the semiconductor feature to form an isolation layer, a first isolated portion comprising the ledge is a first electrode of the pair, a second isolated portion comprising a region of the semiconductor layer facing the ledge is a second electrode of the pair.

5. The method of creating isolated electrodes of claim 4, wherein isolating portions comprises implanting oxygen to form an oxide isolation layer.

6. The method of creating isolated electrodes of claim 1, wherein creating a pair of isolated electrodes comprises:

opening a window in the insulating film adjacent to the ledge to expose the semiconductor layer;

etching the insulating film in the window to undercut the insulating film below the ledge to expose a region of the semiconductor layer, such that the ledge overhangs the insulating film in the opening and cantilevers above the region of the semiconductor layer; and

opening an aperture in the ledge that physically isolates the ledge from the semiconductor layer, wherein the isolated ledge is a first electrode of the pair and the region of the semiconductor layer that faces the isolated ledge is a second electrode of the pair.

7. The method of creating isolated electrodes of claim 6, wherein opening a window in the insulating film comprises using selective anisotropic etching to create vertical sidewalls of the insulating film in the window, and wherein etching the insulating film in the window comprises using selective isotropic etching to form undercuts in the insulating film.

8. The method of creating isolated electrodes of claim 1, wherein the substrate further comprises an insulator layer underneath the semiconductor layer, and wherein creating a pair of isolated electrodes comprises:

opening a first window in the insulating film adjacent to the ledge to expose a portion of the semiconductor layer;

opening second windows through each of the semiconductor features, a portion of the semiconductor layer that underlies the semiconductor feature, and the exposed portion of the semiconductor layer in the first window until the underlying insulator layer is exposed through the second windows, the second windows forming separate columns that each comprises a portion of the semiconductor layer and a portion of the ledge separated by a portion of the insulating film; and

etching the insulating film in the separate column to undercut the insulating film between the ledge and the semiconductor layer, the ledge being a first electrode of the pair, a region the semiconductor layer facing the ledge being a second electrode of the pair.

9. The method of creating isolated electrodes of claim 8, wherein both opening a first window in the insulating film and opening second windows comprises using selective anisotropic etching.

10. The method of creating isolated electrodes of claim 8, wherein opening second windows comprises:

removing both a vertical portion of the semiconductor feature that includes a portion of the ledge above the vertical stem and the vertical stem; and

removing the semiconductor layer that is both below the removed vertical stem and exposed in the first window.

11. The method of creating isolated electrodes of claim 10, wherein removing the semiconductor layer comprises etching the semiconductor layer exposed in the first window either simultaneously with or separately from etching the semiconductor layer that is below the removed vertical stem using directional dry etching.

12. The method of creating isolated electrodes of claim 8, wherein etching the insulating film in the separate column to undercut comprises selective isotropic etching.

13. A method of integrating a nanowire between isolated electrodes of a nanowire-based device comprising:

providing a substrate that comprises a semiconductor layer having a crystal orientation and an insulating film on a surface of the semiconductor layer, the insulating film having a window that exposes a portion of the semiconductor layer surface;

selectively epitaxially growing a semiconductor feature from the semiconductor layer through the window, the semiconductor feature having a vertical stem and a ledge with the crystal orientation of the semiconductor layer, the vertical stem being in contact with the semiconductor layer through the window, the ledge being a lateral epitaxial overgrowth of the vertical stem on the insulating film;

creating a pair of isolated electrodes from the semiconductor feature and the semiconductor layer; and

growing a nanowire to self-assemble between horizontal surfaces of the isolated electrodes of the pair.

14. The method of integrating a nanowire of claim 13, wherein the crystal orientation of the semiconductor layer is a [111] crystal orientation, the horizontal surfaces of the electrodes being (111) surfaces, the nanowire being vertically oriented between the (111) horizontal surfaces, and wherein growing the nanowire comprises using a catalyzed growth technique and a nanoparticle catalyst.

15. The method of integrating a nanowire of claim 13, wherein creating a pair of isolated electrodes comprises etching the insulating film exposed through a gap between ledges of adjacent semiconductor features to remove the insulating film and expose the semiconductor layer;

and embedding an isolation layer into the vertical stem of the semiconductor feature, such that the ledge is electrically isolated from the semiconductor layer, the isolated ledge being a first electrode of the pair and a region of the semiconductor layer that faces the ledge being a second electrode of the pair.

16. The method of integrating a nanowire of claim 13, wherein creating a pair of isolated electrodes comprises:

etching the insulating film exposed through a gap between ledges of adjacent semiconductor features to expose the semiconductor layer;

further etching the insulating film to undercut the insulating film between the ledge and the semiconductor layer; and

etching a portion of the ledge to isolate the ledge from the semiconductor layer, wherein the isolated ledge is a first electrode of the pair and a region of the semiconductor layer that faces the isolated ledge is a second electrode of the pair.

17. The method of integrating a nanowire of claim 13, wherein creating a pair of isolated electrodes comprises:

etching the insulating film exposed through a gap between ledges of adjacent semiconductor features to expose the semiconductor layer;

removing each of a portion of the ledge above the vertical stem, the vertical stem, the semiconductor layer underlying the vertical stem and the exposed semiconductor layer to create an isolated column that comprises the insulating film between the ledge and the semiconductor layer; and

further etching the insulating film to undercut the insulating film between the ledge and the semiconductor layer of the isolated columns, wherein the ledge is a first electrode of the pair and a region of the semiconductor layer that faces the ledge is a second electrode of the pair.