Split gate memory cell in a FinFET
First Claim
Patent Images
1. A memory device, comprising:
- a first semiconductor fin having a first sidewall and a channel region, wherein the channel region includes a portion along the first sidewall and is located between a source region and a drain region, wherein carriers travel substantially horizontally in the channel region;
a select gate structure including a portion adjacent to a first portion of the first sidewall and adjacent to a first portion of the channel region along the first sidewall;
charge storage material at a first location having a first portion adjacent a second portion of the first sidewall and adjacent to a second portion of the channel region along the first sidewall; and
a control gate structure having a first portion adjacent to the first portion of the charge storage material of the first location;
wherein the control gate structure includes a portion located directly over a portion of the select gate structure.
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Abstract
A memory cell is implemented using a semiconductor fin in which the channel region is along a sidewall of the fin between source and drains regions. One portion of the channel region has a select gate adjacent to it and another other portion has the control gate adjacent to it with a charge storage structure there between. In some embodiments, independent control gate structures are located adjacent opposite sidewalls of the fin so as to implement two memory cells.
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Citations
20 Claims
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1. A memory device, comprising:
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a first semiconductor fin having a first sidewall and a channel region, wherein the channel region includes a portion along the first sidewall and is located between a source region and a drain region, wherein carriers travel substantially horizontally in the channel region; a select gate structure including a portion adjacent to a first portion of the first sidewall and adjacent to a first portion of the channel region along the first sidewall; charge storage material at a first location having a first portion adjacent a second portion of the first sidewall and adjacent to a second portion of the channel region along the first sidewall; and a control gate structure having a first portion adjacent to the first portion of the charge storage material of the first location; wherein the control gate structure includes a portion located directly over a portion of the select gate structure. - View Dependent Claims (6, 7, 8, 9, 10, 11, 13, 19, 20)
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2. A memory device, comprising:
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a first semiconductor fin having a first sidewall and a channel region, wherein the channel region includes a portion along the first sidewall and is located between a source region and a drain region, wherein carriers travel substantially horizontally in the channel region; a select pate structure including a portion adjacent to a first portion of the first sidewall and adjacent to a first portion of the channel region along the first sidewall; charge storage material at a first location having a first portion adjacent a second portion of the first sidewall and adjacent to a second portion of the channel region along the first sidewall; a control gate structure having a first portion adjacent to the first portion of the charge storage material at the first location; wherein the first semiconductor fin has a second sidewall opposite the first sidewall, the second sidewall includes a second channel region, the second channel region includes a portion along the second sidewall, wherein carriers travel substantially horizontally in the second channel region; wherein the select gate structure includes a second portion adjacent to a first portion of the second sidewall and adjacent to a first portion of the second channel region along the second sidewall; charge storage material at a second location having a first portion adjacent to a second portion of the second sidewall and adjacent to a second portion of the second channel region along the second sidewall; and a second control gate structure having a first portion adjacent to the first portion of the charge storage material at the second location. - View Dependent Claims (3, 4, 5, 12)
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14. A memory device, comprising:
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a first semiconductor fin having a first sidewall and a channel region, wherein the channel region includes a portion along the first sidewall and is located between a source region and a drain region, wherein carriers travel substantially horizontally in the channel region; a select gate structure including a portion adjacent to a first portion of the first sidewall and adjacent to a first portion of the channel region along the first sidewall; charge storage material at a first location having a first portion adjacent a second portion of the first sidewall and adjacent to a second portion of the channel region along the first sidewall; a control gate structure having a first portion adjacent to the first portion of the charge storage material at the first location; wherein the first semiconductor fin has a second sidewall opposite the first sidewall, the second sidewall includes a second channel region, the second channel region includes a portion along the second sidewall, wherein carriers travel substantially horizontally in the second channel region; a second select gate structure having a portion adjacent to a first portion of the second sidewall and adjacent to a first portion of the second channel region along the second sidewall; charge storage material at a second location having a first portion adjacent to a second portion of the second sidewall and adjacent to a second portion of the second channel region along the second sidewall; and wherein the control gate structure includes a second portion adjacent to the first portion of the charge storage material at the second location.
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15. A memory device, comprising:
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a first semiconductor fin having a first sidewall and a second sidewall, a drain region, a source region, a first channel between the source region and the drain region and along the first sidewall, a second channel between the source region and drain region and along the second sidewall, carriers travel substantially horizontally in the first channel region and the second channel region; a gate dielectric along a first portion of the first sidewall and along a first portion of the second sidewall; a select gate structure on the gate dielectric; charge storage material located along a second portion of the first sidewall and charge storage material located along a second portion of the second sidewall; a first control gate structure having a first portion adjacent to the charge storage material located along the second portion of the first sidewall; and a second control gate structure having a first portion adjacent to the charge storage material located along the second portion of the second sidewall; wherein the first control gate structure includes a portion located directly over a portion of the select gate structure. - View Dependent Claims (16, 17, 18)
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Specification