Split gate memory cell in a FinFET

• US 7,544,980 B2
• Filed: 01/27/2006
• Issued: 06/09/2009
• Est. Priority Date: 01/27/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Swift, Craig T., Chindalore, Gowrishankar L.
• Primary Examiner(s): Smith, Bradley K
• Assistant Examiner(s): Belousov, Alexander
• Application Number:
  US11/342,155
• Publication Number:
  US 20070176223A1
• Time in Patent Office: 1,229 Days
• Field of Search: 257314-326, 257/E29.264, 257/288, 257/619
• US Class Current: 257/288
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 2216/06 Floating gate cells in which the floating gate consists of multiple isolated silicon islands, e.g. nanocrystals
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42348 with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory cell is implemented using a semiconductor fin in which the channel region is along a sidewall of the fin between source and drains regions. One portion of the channel region has a select gate adjacent to it and another other portion has the control gate adjacent to it with a charge storage structure there between. In some embodiments, independent control gate structures are located adjacent opposite sidewalls of the fin so as to implement two memory cells.

Claims

1. A memory device, comprising:

a first semiconductor fin having a first sidewall and a channel region, wherein the channel region includes a portion along the first sidewall and is located between a source region and a drain region, wherein carriers travel substantially horizontally in the channel region;

a select gate structure including a portion adjacent to a first portion of the first sidewall and adjacent to a first portion of the channel region along the first sidewall;

charge storage material at a first location having a first portion adjacent a second portion of the first sidewall and adjacent to a second portion of the channel region along the first sidewall; and

a control gate structure having a first portion adjacent to the first portion of the charge storage material of the first location;

wherein the control gate structure includes a portion located directly over a portion of the select gate structure.

6. The memory device of claim 1 wherein the charge storage material at the first location is implemented in a layer that includes nanoclusters surrounded by dielectric material.

7. The memory device of claim 1, wherein the first semiconductor fin is over a planar insulating surface, wherein the first semiconductor fin comprises monocrystalline silicon.

8. The memory device of claim 1, wherein:

the first semiconductor fin further comprises a second channel region including a portion along the first sidewall of the first semiconductor fin, the first semiconductor fin including a current terminal region located between the channel region and the second channel region, wherein the second channel region includes a portion along the first sidewall, wherein carriers travel substantially horizontally in the second channel region;

a second select gate structure including a portion adjacent to a third portion of the first sidewall and adjacent to a first portion of the second channel region along the first sidewall;

charge storage material at a second location having a first portion adjacent to a fourth portion of the first sidewall and adjacent to a second portion of the second channel region along the first sidewall; and

a second control gate structure having a first portion adjacent to the first portion of the charge storage material at a second location.

9. The memory device of claim 1, wherein:

the source region is located in the first semiconductor fin, and the drain region is located in the semiconductor fin.

10. The memory device of claim 1, wherein:

the first semiconductor fin has a second sidewall opposite the first sidewall;

the select gate structure includes a second portion adjacent to a first portion of the second sidewall;

the memory device further comprising charge storage material at a second location having a first portion along a second portion of the second sidewall;

the control gate structure has a second portion adjacent to the first portion of the charge storage material at a second location.

11. The memory device of claim 10, further comprising:

a second semiconductor fin running substantially parallel to the first semiconductor fin wherein the second semiconductor fin has a first sidewall and a second channel region, wherein the second channel region includes a portion along the first sidewall of the second semiconductor fin, wherein carriers travel substantially horizontally in the second channel region of the second semiconductor fin;

charge storage material at a third location having a first portion along a second portion of the first sidewall of the second semiconductor fin and adjacent to a second portion of the channel region along the first sidewall of the second semiconductor fin;

wherein the select gate structure includes a third portion adjacent to a first portion of the first sidewall of the second semiconductor fin and adjacent to a first portion of the channel region along the first sidewall of the second semiconductor fin; and

wherein the control gate structure has a third portion adjacent to the second portion of the first sidewall of the second semiconductor fin and adjacent to the second portion of the channel region along the first sidewall of the second semiconductor fin;

wherein the first portion of the charge storage material at the third location is disposed between the first sidewall of the second semiconductor fin and the third portion of the control gate structure.

13. The memory device of claim 1 further comprising a dielectric located between the control gate structure and the first semiconductor fin.

19. The memory device of claim 1 wherein the control gate structure includes a portion located directly over a portion of the select gate structure at a location that is lateral to the fin.

20. The memory device of claim 1 wherein the select gate structure includes a structure sidewall that is vertically aligned with a structure sidewall of the control gate structure.

2. A memory device, comprising:

a first semiconductor fin having a first sidewall and a channel region, wherein the channel region includes a portion along the first sidewall and is located between a source region and a drain region, wherein carriers travel substantially horizontally in the channel region;

a select pate structure including a portion adjacent to a first portion of the first sidewall and adjacent to a first portion of the channel region along the first sidewall;

charge storage material at a first location having a first portion adjacent a second portion of the first sidewall and adjacent to a second portion of the channel region along the first sidewall;

a control gate structure having a first portion adjacent to the first portion of the charge storage material at the first location;

wherein the first semiconductor fin has a second sidewall opposite the first sidewall, the second sidewall includes a second channel region, the second channel region includes a portion along the second sidewall, wherein carriers travel substantially horizontally in the second channel region;

wherein the select gate structure includes a second portion adjacent to a first portion of the second sidewall and adjacent to a first portion of the second channel region along the second sidewall;

charge storage material at a second location having a first portion adjacent to a second portion of the second sidewall and adjacent to a second portion of the second channel region along the second sidewall; and

a second control gate structure having a first portion adjacent to the first portion of the charge storage material at the second location.

3. The memory device of claim 2, further comprising:

a second semiconductor fin running substantially parallel to the first semiconductor fin, wherein the second semiconductor fin has a first sidewall and a third channel region, wherein the third channel region includes a portion along the first sidewall of the second semiconductor fin and is located between a source region and a drain region, wherein carriers travel substantially horizontally in the third channel region; and

wherein the select gate structure includes a third portion adjacent to a first portion of the first sidewall of the second semiconductor fin and adjacent to a first portion of the third channel region along the first sidewall of the second semiconductor fin;

charge storage material at a third location having a first portion adjacent to a second portion of the first sidewall of the second semiconductor fin and adjacent to a second portion of the third channel region along the first sidewall of the second semiconductor fin;

wherein a first control gate structure has a second portion adjacent to the first portion of the third charge storage material at the third location.

4. The memory device of claim 2 wherein:

the control gate structure and the channel region serve as a control gate and a channel region for a first memory cell;

the second control gate structure and the second channel region serve as a control gate and a channel region for a second memory cell.

5. The memory device of claim 4 wherein the charge storage material at the first location and the charge storage material at the second location are implemented in a layer of charge storage material.

12. The memory device of claim 2 wherein the control gate structure includes a portion located directly over a portion of the select gate structure.

14. A memory device, comprising:

a first semiconductor fin having a first sidewall and a channel region, wherein the channel region includes a portion along the first sidewall and is located between a source region and a drain region, wherein carriers travel substantially horizontally in the channel region;

a select gate structure including a portion adjacent to a first portion of the first sidewall and adjacent to a first portion of the channel region along the first sidewall;

charge storage material at a first location having a first portion adjacent a second portion of the first sidewall and adjacent to a second portion of the channel region along the first sidewall;

a control gate structure having a first portion adjacent to the first portion of the charge storage material at the first location;

wherein the first semiconductor fin has a second sidewall opposite the first sidewall, the second sidewall includes a second channel region, the second channel region includes a portion along the second sidewall, wherein carriers travel substantially horizontally in the second channel region;

a second select gate structure having a portion adjacent to a first portion of the second sidewall and adjacent to a first portion of the second channel region along the second sidewall;

charge storage material at a second location having a first portion adjacent to a second portion of the second sidewall and adjacent to a second portion of the second channel region along the second sidewall; and

wherein the control gate structure includes a second portion adjacent to the first portion of the charge storage material at the second location.

15. A memory device, comprising:

a first semiconductor fin having a first sidewall and a second sidewall, a drain region, a source region, a first channel between the source region and the drain region and along the first sidewall, a second channel between the source region and drain region and along the second sidewall, carriers travel substantially horizontally in the first channel region and the second channel region;

a gate dielectric along a first portion of the first sidewall and along a first portion of the second sidewall;

a select gate structure on the gate dielectric;

charge storage material located along a second portion of the first sidewall and charge storage material located along a second portion of the second sidewall;

a first control gate structure having a first portion adjacent to the charge storage material located along the second portion of the first sidewall; and

a second control gate structure having a first portion adjacent to the charge storage material located along the second portion of the second sidewall;

wherein the first control gate structure includes a portion located directly over a portion of the select gate structure.

16. The memory device of claim 15 wherein the charge storage material located along a second portion of the first sidewall and the charge storage material located along a second portion of the second sidewall each include nanoclusters.

17. The memory device of claim 15 further comprising:

a second semiconductor fin having a first sidewall and a second sidewall, a drain region, a source region, a first channel between the source region and the drain region and along the first sidewall of the second semiconductor fin, a second channel between the source region and drain region and along the second sidewall of the second semiconductor fin, carriers travel substantially horizontally in the first channel region and the second channel region of the second semiconductor fin;

a second gate dielectric along a first portion of the first sidewall of the second semiconductor fin and along a first portion of the second sidewall of the second semiconductor fin, wherein the select gate structure on the second gate dielectric;

charge storage material located along a second portion of the first sidewall of the second semiconductor fin and charge storage material located along a second portion of the second sidewall of the second semiconductor fin;

wherein the first control gate structure has a second portion adjacent to the charge storage material located along the second portion of the first sidewall of the second semiconductor fin.

18. The memory device of claim 15 wherein the select gate structure includes a structure sidewall that is vertically aligned with a structure sidewall of the control gate structure.