Gettering using voids formed by surface transformation
First Claim
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1. A memory device, comprising:
- at least one gettering region formed in a semiconductor substrate, the gettering region including a predetermined arrangement of precisely-formed voids to getter impurities from a crystalline semiconductor region of the substrate, wherein;
the predetermined arrangement of precisely-formed voids are formed using a surface transformation process to transform holes or trenches formed with predetermined dimensions and spacing through a surface of a material with a defined melting temperature to form the plurality of precisely formed voids within the material; and
the predetermined arrangement of the plurality of precisely-formed voids includes voids with a predetermined size, shape and spacing controlled by the predetermined dimensions and spacing of the trenches or holes;
a memory array formed in the crystalline semiconductor region, including a plurality of memory cells formed in rows and columns, and at least one transistor for each of the plurality of memory cells;
a plurality of word lines, each word line being connected to a row of memory cells;
a plurality of bit lines, each bit line being connected to a column of memory cells; and
control circuitry, including word line select circuitry and bit line select circuitry to select a number of memory cells for writing and reading operations.
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Abstract
One aspect of this disclosure relates to a memory device, comprising at least one gettering region, a memory array, a plurality of word lines and bit lines, and control circuitry. The gettering region is formed in a semiconductor substrate. The gettering region includes a precise arrangement of precisely-formed voids to getter impurities from a crystalline semiconductor region of the substrate. The memory array is formed in the crystalline semiconductor region, and includes a plurality of memory cells formed in rows and columns, and at least one transistor for each of the plurality of memory cells. Each word line is connected to a row of memory cells, and each bit line is connected to a column of memory cells. The control circuitry includes word line select circuitry and bit line select circuitry to select a number of memory cells for writing and reading operations.
112 Citations
21 Claims
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1. A memory device, comprising:
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at least one gettering region formed in a semiconductor substrate, the gettering region including a predetermined arrangement of precisely-formed voids to getter impurities from a crystalline semiconductor region of the substrate, wherein; the predetermined arrangement of precisely-formed voids are formed using a surface transformation process to transform holes or trenches formed with predetermined dimensions and spacing through a surface of a material with a defined melting temperature to form the plurality of precisely formed voids within the material; and the predetermined arrangement of the plurality of precisely-formed voids includes voids with a predetermined size, shape and spacing controlled by the predetermined dimensions and spacing of the trenches or holes; a memory array formed in the crystalline semiconductor region, including a plurality of memory cells formed in rows and columns, and at least one transistor for each of the plurality of memory cells; a plurality of word lines, each word line being connected to a row of memory cells; a plurality of bit lines, each bit line being connected to a column of memory cells; and control circuitry, including word line select circuitry and bit line select circuitry to select a number of memory cells for writing and reading operations. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory device, comprising:
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at least one gettering region formed in a semiconductor substrate, the gettering region including a precise arrangement of precisely-formed voids to getter impurities from a crystalline semiconductor region of the substrate, wherein the plurality of voids are separated by a critical length (λ
C) that is dependent on a radius (RC) of a number of holes used to form the plurality of voids using a surface transformation process, and the plurality of precisely-formed voids includes a sphere-shaped voida memory array formed in the crystalline semiconductor region, including a plurality of memory cells formed in rows and columns, and at least one transistor for each of the plurality of memory cells; a plurality of word lines, each word line being connected to a row of memory cells; a plurality of bit lines, each bit line being connected to a column of memory cells; and control circuitry, including word line select circuitry and bit line select circuitry to select a number of memory cells for writing and reading operations. - View Dependent Claims (10, 11, 12)
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13. A memory device, comprising:
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at least one gettering region formed in a semiconductor substrate, the gettering region including a precise arrangement of precisely-formed voids to getter impurities from a crystalline semiconductor region of the substrate, wherein the plurality of voids are separated by a critical length (λ
C) that is dependent on a radius (RC) of a number of holes used to form the plurality of voids using a surface transformation process, and the plurality of precisely-formed voids includes a pipe-shaped void;a memory array formed in the crystalline semiconductor region, including a plurality of memory cells formed in rows and columns, and at least one transistor for each of the plurality of memory cells; a plurality of word lines, each word line being connected to a row of memory cells; a plurality of bit lines, each bit line being connected to a column of memory cells; and control circuitry, including word line select circuitry and bit line select circuitry to select a number of memory cells for writing and reading operations. - View Dependent Claims (14, 15, 16)
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17. A memory device, comprising:
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at least one gettering region formed in a semiconductor substrate, the gettering region including a precise arrangement of precisely-formed voids to getter impurities from a crystalline semiconductor region of the substrate, wherein the plurality of voids are separated by a critical length (λ
C) that is dependent on a radius (RC) of a number of holes used to form the plurality of voids using a surface transformation process, and the plurality of precisely-formed voids includes a plate-shaped void;a memory array formed in the crystalline semiconductor region, including a plurality of memory cells formed in rows and columns, and at least one transistor for each of the plurality of memory cells; a plurality of word lines, each word line being connected to a row of memory cells; a plurality of bit lines, each bit line being connected to a column of memory cells; and control circuitry, including word line select circuitry and bit line select circuitry to select a number of memory cells for writing and reading operations. - View Dependent Claims (18, 19, 20)
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21. A memory device, comprising:
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at least one gettering region formed in a semiconductor substrate, the gettering region including a precise arrangement of precisely-formed voids to getter impurities from a crystalline semiconductor region of the substrate; a memory array formed in the crystalline semiconductor region, including a plurality of memory cells formed in rows and columns, and at least one transistor for each of the plurality of memory cells; a plurality of word lines, each word line being connected to a row of memory cells; a plurality of bit lines, each bit line being connected to a column of memory cells; and control circuitry, including word line select circuitry and bit line select circuitry to select a number of memory cells for writing and reading operations, wherein the plurality of voids are separated by a critical length (λ
C) that is dependent on a radius (RC) of a number of holes used to form the plurality of voids using a surface transformation process.
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Specification
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Current AssigneeMicron Technology, Inc.
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Original AssigneeMicron Technology, Inc.
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InventorsForbes, Leonard, Geusic, Joseph E.
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Primary Examiner(s)Quach; Tuan N.
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Application NumberUS11/606,479Publication NumberTime in Patent Office922 DaysField of Search257/204, 257/208, 257/296, 257/629, 257618-621, 257/E29.107, 257/E27.084US Class Current257/296CPC Class CodesH01L 21/3223 using cavities formed by hy...H01L 21/324 Thermal treatment for modif...H01L 27/105 including field-effect comp...H01L 29/78 with field effect produced ...H10B 12/00 Dynamic random access memor...Y10S 257/913 with means to absorb or loc...
