Method and structure for forming strained devices

• US 7,545,004 B2
• Filed: 04/12/2005
• Issued: 06/09/2009
• Est. Priority Date: 04/12/2005
• Status: Expired due to Fees

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.), International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lim, Eng Hua, Yang, Haining S.
• Primary Examiner(s): Menz; Douglas M
• Assistant Examiner(s): Such; Matthew W
• Application Number:
  US10/907,689
• Publication Number:
  US 20060228836A1
• Time in Patent Office: 1,519 Days
• Field of Search: 257/255, 257/371, 257/389, 257/632, 257/635, 257/640, 257/649, 257/369, 257E29106-E29108, 257E2501-E25012, 438/199, 438/761, 438/763, 438/791
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects

Abstract

A method for manufacturing a device includes mapping extreme vertical boundary conditions of a mask layer based on vertical edges of a deposited first layer and a second layer. The mask layer is deposited over portions of the second layer based on the mapping step. The exposed area of the second layer is etched to form a smooth boundary between the first layer and the second layer. The resist layer is stripped. The resulting device is an improved PFET device and NFET device with a smooth boundary between the first and second layers such that a contact can be formed at the smooth boundary without over etching other areas of the device.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having at least one p-type device and one n-type device;

a first strain layer imposing a compressive stress in the p-type device;

a second strain layer imposing a tensile stress in the n-type device;

a smooth boundary provided between the first strain layer and the second strain layer;

a dielectric layer deposited over the first strain layer and the second strain layer, including the smooth boundary; and

at least one via contact formed in the dielectric layer and connecting to one of the n-type device and p-type device at the smooth boundary,

wherein one of the at least one via contact is in contact with the first strain layer and the second strain layer, and

wherein the smooth boundary is devoid of overlaps.

2. The device of claim 1 wherein the smooth boundary is devoid of gaps.

3. The device of claim 1 wherein the at least one via contact is plural via contacts, the plural via contacts contacting the n-type device and p-type device at the smooth boundary and at locations other than the smooth boundary.

4. A semiconductor device, comprising:

a semiconductor substrate having at least one p-type device and one n-type device;

a first strain layer imposing a compressive stress in the p-type device;

a second strain layer imposing a tensile stress in the n-type device;

a smooth boundary provided between the first strain layer and the second strain layer;

a dielectric layer deposited over the first strain layer and the second strain layer, including the smooth boundary; and

at least one via contact formed in the dielectric layer and connecting to one of the n-type device and p-type device at the smooth boundary,

wherein one of the at least one via contact is in contact with the first strain layer and the second strain layer, and

wherein the smooth boundary is defined as abutting ends of the first strain layer and the second strain layer.