Semiconductor device with a wiring substrate and method for producing the same

• US 7,545,047 B2
• Filed: 11/06/2006
• Issued: 06/09/2009
• Est. Priority Date: 05/06/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Woerner, Holger, Fuergut, Edward, Bauer, Michael, Jerebic, Simon
• Primary Examiner(s): Huynh; Andy
• Application Number:
  US11/593,150
• Publication Number:
  US 20070126122A1
• Time in Patent Office: 946 Days
• Field of Search: 257/686, 257/737, 257/738, 257/774, 257/778, 257/E21.705, 257/E25.023
• US Class Current: 257/774
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/82039 : using a laser
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/107 : Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB printed circuits H05K1/00
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/0101 : Neon [Ne]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01052 : Tellurium [Te]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor device with a wiring substrate as a stacking element for a semiconductor device stack is described herein. The wiring substrate includes a plastic frame of a first plastic compound and a central region of a second plastic compound. A semiconductor chip is embedded with its back side and its edge sides in the second plastic compound, the active upper side of the semiconductor device being in a coplanar area with the first and second plastic compounds.

Claims

1. A semiconductor device comprising:

a wiring substrate operable as a stacking element for a semiconductor device stack, the wiring substrate forming an underside and an upper side of the semiconductor device, the wiring substrate comprising;

a plastic frame of a first plastic compound, the plastic frame being disposed in an edge region that surrounds a central region of the semiconductor device; and

a second plastic compound disposed in the central region;

a plurality of external contact pads disposed on the underside and the upper side of the wiring substrate and arranged in at least the edge region of the wiring substrate;

a plurality of contact vias extending through the wiring substrate and electrically connecting upper side external contact pads to underside external contact pads; and

a semiconductor chip including an active upper side with chip contact areas, the semiconductor chip embedded with its back side and its edge sides in the volume of the wiring substrate, the semiconductor chip being at least partially surrounded by the contact vias;

wherein the underside of the wiring substrate with underside external contact pads and the active upper side of the semiconductor chip with chip contact areas form a coplanar area.

2. The semiconductor device according to claim 1, wherein the coplanar area is covered by an insulating layer including windows exposing the chip contact areas and the underside external contact pads of the wiring substrate.

3. The semiconductor device according to claim 1, wherein the coplanar area carries a structured wiring layer with wiring lines, the structured wiring layer extending between underside external contact pads of the wiring substrate and chip contact areas of the semiconductor chip.

4. The semiconductor device according to claim 3, wherein the structured wiring layer is covered by a solder resist layer such that the solder resist layer allows access to the underside external contact pads of the wiring substrate.

5. The semiconductor device according to claim 1, wherein the underside external contact pads of the wiring substrate comprise semiconductor device external contacts.

6. The semiconductor device according to claim 5, wherein the semiconductor device external contacts comprise solder balls.

7. The semiconductor device according to claim 1, wherein the upper side of the wiring substrate comprises a structured wiring layer electrically connecting the upper side external contact pads in the edge region of the wiring substrate to external semiconductor device contact pads disposed on the entire upper side of the semiconductor device, the upper side external semiconductor device contact pads being arranged in positions of a predetermined array corresponding to positions of underside semiconductor device external contacts of a semiconductor device to be stacked.

8. A semiconductor device module comprising:

a stack of semiconductor devices, the stack including a semiconductor device according to claim 1 as a stacking element.

9. A semiconductor device module comprising:

a stack of semiconductor devices, the stack including a semiconductor device according to claim 1 as a semiconductor base component.

10. The semiconductor device module according to claim 9, wherein the coplanar area carries a structured wiring layer with wiring lines, the structured wiring layer extending between underside external contact pads of the wiring substrate and chip contact areas of the semiconductor chip.

11. The semiconductor device module according to claim 9,

wherein the stack further comprises a wiring structure disposed on an upper side of the stack, the wiring structure including at least one further device electrically connected to the semiconductor devices of the stack via the wiring structure;

wherein the at least one further device is one of;

a passive device and a surface-mountable semiconductor device.

12. The semiconductor device module according to claim 9, wherein the stacked semiconductor device further comprises an internal chip stack comprising a plurality of semiconductor chips wherein at least one of the semiconductor chips comprises flip-chip contacts.

13. The semiconductor device module according to claim 9, wherein the stack comprises a plurality of stacked semiconductor devices the same type, each of the stacked semiconductor devices including a coplanar area that carries a structured wiring layer with wiring lines, the structured wiring layer extending between underside external contact pads of a wiring substrate and chip contact areas of a semiconductor chip.

14. A panel for a plurality of semiconductor devices according to claim 1, the panel comprising at least one device position on a removable carrier film.

15. The semiconductor device of claim 1, wherein the plastic frame in the edge region and the second plastic compound in the central region extend from the coplanar underside of the wiring substrate to the upper side of the wiring substrate.

16. The semiconductor device of claim 1, wherein the contact vias extend through the plastic frame in the edge region of the wiring substrate.

17. The semiconductor device of claim 1, wherein the semiconductor chip is disposed within the central region and is embedded in the second plastic compound on its back and sides faces.