Graphics display system with video synchronization feature

• US 7,545,438 B2
• Filed: 04/23/2007
• Issued: 06/09/2009
• Est. Priority Date: 11/09/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: MacInnis, Alexander G., Tang, Chengfuh Jeffrey, Kranawetter, Greg A., Patterson, James T., Xie, Xiaodong
• Primary Examiner(s): Natnael; Paulos M
• Application Number:
  US11/738,870
• Publication Number:
  US 20070285440A1
• Time in Patent Office: 778 Days
• Field of Search: 348/441, 348512-517, 348/536, 348/540, 348/547
• US Class Current: 348/441
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 9/00 Image coding bandwidth or redundancy reduction for static pictures H04N1/41; coding or decoding of static colour picture signals H04N1/64; methods or arrangements for coding, decoding, compressing or decompressing digital video signals H04N19/00
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/02 : characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/024 : using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/026 : Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/06 : using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/12 : Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/14 : Display of multiple viewports
• CPC Class Codes: G09G 5/28 : for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/346 : for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/36 : characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: G09G 5/363 : Graphics controllers
• CPC Class Codes: H04N 11/143 : Encoding means therefor H04N11/16 takes precedence
• CPC Class Codes: H04N 11/20 : Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 19/42 : characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 : characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 : using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 : Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/59 : involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 21/42204 : User interfaces specially adapted for controlling a client device through a remote control device; Remote control devices therefor constructive details of casings for the remote control device H01H9/0235; user interfaces for controlling a tuning device of a television receiver through a remote control H03J9/00; remote control of peripheral devices connected to a television receiver through the remote control device of the television receiver H04B1/205
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42653 : for processing graphics
• CPC Class Codes: H04N 21/4305 : Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4316 : for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/434 : Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/440263 : by altering the spatial resolution, e.g. for displaying on a connected PDA
• CPC Class Codes: H04N 21/4438 : Window management, e.g. event handling following interaction with the user interface
• CPC Class Codes: H04N 21/47 : End-user applications
• CPC Class Codes: H04N 5/04 : Synchronising for television systems using pulse code modulation H04N7/56
• CPC Class Codes: H04N 5/126 : whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 5/14 : Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 : Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/0122 : the input and the output signals having different aspect ratios
• CPC Class Codes: H04N 7/0135 : involving interpolation processes interpolation-based image scaling G06T3/4007; interpolation for video coding H04N19/587, H04N19/59
• CPC Class Codes: H04N 9/45 : Generation or recovery of colour sub-carriers
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H04N 9/642 : Multi-standard receivers

Abstract

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. The system includes a video decoder having a chroma-locked sample rate converter. The chroma-locked sample rate converter converts the samples to those taken at a sample rate that is a multiple of the chroma subcarrier frequency and that is locked to chroma bursts of the analog video signal in a control loop. The video decoder also includes a line-locked sample rate converter that receives samples at a multiple of the chroma subcarrier frequency and converts the samples to samples with a sample frequency that is a multiple of the horizontal line rate of the video input. The line-locked sample rate converter measures the horizontal line rate to an accuracy of a fraction of a pixel and adjusts the sample rate and phase of the line-locked sample rate converter to produce accurate line-locked samples. The time base corrector receives samples at the output of the line-locked sample rate converter and provides samples synchronized to the display clock for reducing undesirable artifacts such as jitter.

Claims

1. A video synchronizing mechanism comprising:

a first sample rate converter for converting a stream of input video samples having an input sample rate to first video samples having a first converted rate;

a filter for processing at least one of the first video samples having the first converted rate;

a second sample rate converter for converting the first video samples having the first converted rate to second video samples having a second converted rate; and

a time base corrector comprising a FIFO for receiving the second video samples and for synchronizing the second video samples to a display clock to provide output video samples that are synchronous to the display clock; and

wherein the FIFO has a size of a horizontal line.

2. The video synchronizing mechanism of claim 1 wherein the time base corrector further comprises a time base corrector controller for controlling the FIFO to convert the second video samples to the output video samples.

3. The video synchronizing mechanism of claim 1 wherein the FIFO is filled with the second video samples to approximately one-half of its size prior to start providing the output video samples.

4. The video synchronizing mechanism of claim 2 wherein the time base corrector controller generates vertical syncs for the output video samples.

5. The video synchronizing mechanism of claim 4 wherein the time base corrector controller derives timing signals from the vertical syncs, and the timing signals include horizontal syncs.

6. The video synchronizing mechanism of claim 1 wherein the FIFO is filled with the second video samples to more than one-half of its size prior to start providing the output video samples.

7. The video synchronizing mechanism of claim 1 wherein the FIFO is filled with the second video samples to less than one-half of its size prior to start providing the output video samples.

8. A video synchronizing mechanism comprising:

a first sample rate converter for converting a stream of input video samples having an input sample rate to first video samples having a first converted rate;

a filter for processing at least one of the first video samples having the first converted rate;

a second sample rate converter for converting the first video samples having the first converted rate to second video samples having a second converted rate; and

a time base corrector comprising a FIFO for receiving the second video samples and for synchronizing the second video samples to a display clock to provide output video samples that are synchronous to the display clock; and

wherein the FIFO has a size larger than a horizontal line.

9. The video synchronizing mechanism of claim 8 wherein the time base corrector further comprises a time base corrector controller for controlling the FIFO to convert the second video samples to the output video samples.

10. The video synchronizing mechanism of claim 9 wherein the time base corrector controller generates vertical syncs for the output video samples.

11. The video synchronizing mechanism of claim 10 wherein the time base corrector controller derives timing signals from the vertical syncs, and the timing signals include horizontal syncs.

12. The video synchronizing mechanism of claim 8 wherein the FIFO is filled with the second video samples to approximately one-half of its size prior to start providing the output video samples.

13. The video synchronizing mechanism of claim 8 wherein the FIFO is filled with the second video samples to more than one-half of its size prior to start providing the output video samples.

14. The video synchronizing mechanism of claim 8 wherein the FIFO is filled with the second video samples to less than one-half of its size prior to start providing the output video samples.

15. A video synchronizing mechanism comprising:

a first sample rate converter for converting a stream of input video samples having an input sample rate to first video samples having a first converted rate;

a filter for processing at least one of the first video samples having the first converted rate;

a second sample rate converter for converting the first video samples having the first converted rate to second video samples having a second converted rate; and

a time base corrector comprising a FIFO for receiving the second video samples and for synchronizing the second video samples to a display clock to provide output video samples that are synchronous to the display clock; and

wherein the FIFO has a size smaller than a horizontal line.

16. The video synchronizing mechanism of claim 15 wherein the time base corrector further comprises a time base corrector controller for controlling the FIFO to convert the second video samples to the output video samples.

17. The video synchronizing mechanism of claim 16 wherein the time base corrector controller generates vertical syncs for the output video samples.

18. The video synchronizing mechanism of claim 17 wherein the time base corrector controller derives timing signals from the vertical syncs, and the timing signals include horizontal syncs.

19. The video synchronizing mechanism of claim 15 wherein the FIFO is filled with the second video samples to approximately one-half of its size prior to start providing the output video samples.

20. The video synchronizing mechanism of claim 15 wherein the FIFO is filled with the second video samples to more than one-half of its size prior to start providing the output video samples.

21. The video synchronizing mechanism of claim 15 wherein the FIFO is filled with the second video samples to less than one-half of its size prior to start providing the output video samples.