Efficient AAL5-based mechanism for handling voice ATM cells to significantly reduce CPU load

• US 7,545,828 B2
• Filed: 04/07/2003
• Issued: 06/09/2009
• Est. Priority Date: 06/21/2002
• Status: Active Grant

• Current Assignee: ADTRAN Incorporated (ADTRAN Holdings, Inc.)
• Original Assignee: ADTRAN Incorporated (ADTRAN Holdings, Inc.)
• Inventors: Herron, Phillip Stone
• Primary Examiner(s): Kizou; Hassan
• Assistant Examiner(s): Moutaouakil; Mounir
• Application Number:
  US10/408,590
• Publication Number:
  US 20030235199A1
• Time in Patent Office: 2,255 Days
• Field of Search: 370/498, 370/508, 370/419, 370/463, 370/545, 370/321, 370/326, 370/347, 370/442, 370/458, 370/337, 370466-467, 709/250
• US Class Current: 370/466
• CPC Class Codes: H04L 2012/5671 Support of voice
• CPC Class Codes: H04L 49/20 Support for services
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3081 ATM peripheral units, e.g. policing, insertion or extraction

Abstract

A mechanism for implementing a single-interrupt-based voice playout buffer transfer operation. The contents of each respective channel of a multi-channel voice playout buffer are encapsulated so as to prepend a four byte ATM header, a HEC byte, and a four byte AAL2 header to a forty-four byte voice channel field to realize a standard fifty-three byte ATM cell. Within the AAL2 header, a channel identification byte (CID) provides selective mapping to timeslots of a TDM frame, to accommodate variations among different vendor equipments. The next to last bit of the last byte of the ATM header is used as an interrupt to the network processor. Only the highest voice channel asserts this next to last bit as an interrupt bit.

Claims

1. A digital telecommunication apparatus comprising:

a host network processor configured to be coupled to data terminal equipment;

a multi-protocol communication interface, which is operative to execute diverse types of digital communication signaling interface functions with a plurality of communication ports, under the control of supervisory control signals supplied by said host network processor, said plurality of communication ports including a first port configured to interface ATM cell-based voice and data traffic with a digital communication network, a second port configured to interface TDM voice communication signals with a time division multiplexed (TDM) digitized voice communication link, and a third port configured to be coupled with a dual PHY ATM cell-based communication path over which ATM cell-based communications containing communication signals interfaced at said first and second ports are conducted between said multi-protocol communication interface and said host network processor;

said multi-protocol communication interface includes a bidirectional digital cross-connect switch coupled to said second port, and providing TDM voice signaling connectivity between said second port and an internal TDM bus, said internal TDM bus being coupled with said dual PHY ATM cell-based communication path in such a manner as to interface TDM voice signals at said second port as ATM cell-based voice communications over said dual PHY ATM cell-based communication path with said host network processor;

said bidirectional digital cross-connect switch is further coupled to said first port, and wherein said multi-protocol communication interface is configured to interface ATM cell-based voice communications received over said dual PHY ATM cell-based communication path from said host network processor through said bidirectional digital cross-connect switch with said first port for application to said digital communication network; and

a cell encapsulation logic unit configured to perform header prepending operations.

2. The digital communications apparatus according to claim 1, wherein cell encapsulation unit performs first and second header prepending operations.

3. The digital communications apparatus according to claim 2, wherein said first header prepending operation assembles a four byte ATM Adaptation Layer 2 (AAL2) header.

4. The digital communications apparatus according to claim 3, wherein said four byte AAL2 header incorporates a channel identification field or CID.

5. The digital communications apparatus according to claim 2, wherein said second header prepending operation assembles a four byte ATM header.

6. The digital communications apparatus according to claim 3, wherein a next to last bit comprises an interrupt bit that selectively interrupts the host network processor.

7. A digital telecommunication apparatus comprising:

a host network processor configured to be coupled to data terminal equipment;

a multi-protocol communication interface, which is operative to execute diverse types of digital communication signaling interface functions with a plurality of communication ports, under the control of supervisory control signals supplied by said host network processor, said plurality of communication ports including a first port configured to interface ATM cell-based voice and data traffic with a digital communication network, a second port configured to interface TDM voice communication signals with a time division multiplexed (TDM) digitized voice communication link, and a third port configured to be coupled with a dual PHY ATM cell-based communication path over which ATM cell-based communications containing communication signals interfaced at said first and second ports are conducted between said multi-protocol communication interface and said host network processor;

said multi-protocol communication interface includes a bidirectional digital cross-connect switch coupled to said second port, and providing TDM voice signaling connectivity between said second port and an internal TDM bus, said internal TDM bus being coupled with said dual PHY ATM cell-based communication path in such a manner as to interface TDM voice signals at said second port as ATM cell-based voice communications over said dual PHY ATM cell-based communication path with said host network processor;

said internal TDM bus is coupled with a voice gateway having a first, TDM legacy port for providing access to a TDM voice legacy circuit, and having a second, TDM throughput port coupled with a full duplex digitized voice signal playout buffer unit that is operative to interface TDM voice signals transported by said internal TDM bus as ATM-cell based voice communications over said dual PHY ATM cell-based communication path with said host network processor; and

a cell encapsulation logic unit configured to perform header prepending operations.

8. The digital communications apparatus according to claim 7, wherein cell encapsulation unit performs first and second header prepending operations.

9. The digital communications apparatus according to claim 8, wherein said first header prepending operation assembles a four byte ATM Adaptation Layer 2 (AAL2) header.

10. The digital communications apparatus according to claim 9, wherein said four byte AAL2 header incorporates a channel identification field or CID.

11. The digital communications apparatus according to claim 8, wherein said second header prepending operation assembles a four byte ATM header.

12. The digital communications apparatus according to claim 11, wherein a next to last bit comprises an interrupt bit that selectively interrupts the host network processor.

13. A digital telecommunication apparatus comprising:

a first port configured to be coupled to a digital communication network;

a second port configured to be coupled to a time division multiplexed (TDM) digitized voice communication link;

a third port configured to be coupled with a cell-based communication path, over which cell-based digital communications are conducted with a host processor; and

a multi-protocol communication interface coupled to said first, second and third ports, and being operative

to interface digital communication signal traffic received at said first port and TDM digitized voice signal traffic received at said second port, as cell-based digital communication signals for application to said third port and transport therefrom over said cell-based communication path to said host processor, and

to interface each of cell-based digital communication signal traffic and cell-based digitized voice communication signals, received at said third port from said host processor via said cell-based communication path, and destined for delivery to a communication circuit served by said digital communication network, as digitized communication signals for application from said first port to said digital communication network wherein

said multi-protocol communication interface further includes a digital communication network-to-TDM voice communication link transport path, which is operative to interface digitized voice signals, received at said first port from said digital communication network and destined for delivery to a voice signaling circuit served by said TDM voice communication link, with said third port and transport therefrom as cell-based digitized voice signals over said cell-based communication path to said host processor, and to interface cell-based digitized voice signals, supplied to said third port over said cell-based communication path from said host processor and destined for delivery to said voice signaling circuit served by said TDM voice communication link, as TDM digitized voice signals for application from said second port and transport via said TDM voice communication link to said voice signaling circuit; and

a cell encapsulation logic unit configured to perform header prepending operations.

14. The digital communications apparatus according to claim 13, wherein cell encapsulation unit performs first and second header prepending operations.

15. The digital communications apparatus according to claim 14, wherein said first header prepending operation assembles a four byte ATM Adaptation Layer 2 (AAL2) header.

16. The digital communications apparatus according to claim 15, wherein said four byte AAL2 header incorporates a channel identification field or CID.

17. The digital communications apparatus according to claim 14, wherein said second header prepending operation assembles a four byte ATM header.

18. The digital communications apparatus according to claim 17, wherein a next to last bit comprises an interrupt bit that selectively interrupts the host network processor.