Optical storage system comprising interface for transferring data

• US 7,546,402 B2
• Filed: 03/24/2005
• Issued: 06/09/2009
• Est. Priority Date: 03/24/2005
• Status: Active Grant

• Current Assignee: Sunplus Technology Co., Ltd
• Original Assignee: Sunplus Technology Co., Ltd
• Inventors: Lee, Yu-Chu, Chen, Wen-Kuan
• Primary Examiner(s): Tsai, Henry W. H.
• Assistant Examiner(s): RHU, KRIS M
• Application Number:
  US11/087,624
• Publication Number:
  US 20060218323A1
• Time in Patent Office: 1,538 Days
• Field of Search: 710/65, 725/132, 725/133, 360/39, 360/49
• US Class Current: 710/71
• CPC Class Codes: G11B 20/10 Digital recording or reproducing

Abstract

An optical storage system for coupling to at least a plurality of peripheral devices. The optical storage system includes a data read subsystem to read out data stored in an optical storage medium, a data process subsystem to generate address information and data information according to the read out data, and an interface controller to generate output data according to the address information and the data information and to transfer the output data to one of the peripheral devices. A number of bits of the output data being transferred in parallel is configurable according to a parallel bit number. The data information and the address information are transferred via the same pins.

Claims

1. An optical storage system for coupling to at least a peripheral device, comprising:

a data read subsystem to read out data stored in an optical storage medium;

a data process subsystem to process the read out data and to generate data information and address information according to the read out data;

a plurality of pins; and

an interface controller to generate output data according to the data information and the address information and to transfer the output data to the peripheral device, wherein a number of bits of the output data being transferred in parallel is configurable according to a parallel bit number, and the data information and the address information are transferred via the same pins, the interface controller comprising;

an address decoder to decode and output the address information;

a control register to determine the peripheral device to which the output data is to be transferred according to the decoded address information, and to determine the parallel bit number according to the peripheral device to which the output data is to be transferred;

an output buffer to store the data information; and

an interface encoder to generate the output data according to the data information and the address information.

2. The system of claim 1, wherein the parallel bit number is determined by the interface controller.

3. The system of claim 2, wherein the parallel bit number is one of 1, 2, 4, and 8.

4. The system of claim 2, wherein the parallel bit number is determined according to the peripheral device to which output data is to be transferred.

5. The system of claim 1, wherein the interface encoder further divides the output data into a plurality of sets of sub-data according to the parallel bit number, the number of sets of sub-data being the same as the parallel bit number.

6. The system of claim 5, wherein the interface outputs the sets of sub-data in parallel.

7. The system of claim 6, wherein the output data is compatible with a serial peripheral interface (SPI) standard.

8. The system of claim 7, wherein the output data further includes at least a command data, an address data, and a plurality of data blocks, and each of the sets of sub-data further includes at least part of the command data, part of the address data, and part of the data blocks.

9. The system of claim 7, wherein the output data further includes a dummy data cycle and each of the sets of sub-data further includes a sub-dummy data cycle, wherein the sub-dummy data cycle is determined according to the peripheral device to which the output data is to be transferred.

10. The system of claim 9, wherein the sub-dummy data cycle is configurable according to a result of comparing the output data and data sent back by the peripheral device after receiving the output data.

11. The system of claim 1, wherein the pins are for receiving input data from the peripheral device, and wherein a number of bits of the input data received in parallel is determined according to the parallel bit number.

12. The system of claim 11, wherein the data process subsystem further comprises a data collector to receive the input data and an input buffer to store the input data.

13. The system of claim 1, wherein one of the peripheral devices to which the optical storage system can be coupled is a non-volatile memory.

14. The system of claim 1, wherein the optical storage system is a digital video disk (DVD) system.

15. The system of claim 1, wherein the optical storage system is a digital video compact disc (VCD) system.

16. A method for transferring data between an optical storage system including a plurality of pins and a peripheral device coupled to the optical storage system by an interface, comprising:

reading out data stored in an optical storage medium;

generating data information and address information according to the read out data;

generating output data according to the address information and the data information, comprising;

decoding the address information;

determining the peripheral device to which the output data is to be transferred according to the decoded address information;

determining a parallel bit number according to the peripheral device to which the output data is to be transferred;

storing the data information; and

generating the output data according to the data information and the address information; and

transferring the output data to the peripheral device, wherein a number of bits of the output data being transferred is configurable according to the parallel bit number, and the address information and the data information are transferred via the same pins.

17. The method of claim 16, wherein determining includes determining the parallel bit number to be one of 1, 2, 4, and 8.

18. The method of claim 16, wherein the parallel bit number corresponding to the peripheral device is predetermined.

19. The method of claim 16, wherein generating the output data further comprises dividing the output data into a plurality of sets of sub-data according to the parallel bit number, the number of sets of sub-data being the same as the parallel bit number.

20. The method of claim 19, wherein transferring includes transferring the sets of sub-data in parallel.

21. The method of claim 19, wherein the output data is compatible with a serial peripheral interface (SPI) standard, and

generating includes generating the output data to include at least a command data, an address data, and a plurality of data blocks.

22. The method of claim 21, wherein generating the output data further comprises:

dividing the command data into a plurality of sub-command data;

dividing the address data into a plurality of sub-address data;

dividing the data blocks into a plurality of sub-data blocks; and

generating each sub-data set according to one of the sub-command data, one of the sub-address data, and at least one of the sub-data blocks.

23. The method of claim 21, wherein generating the output data further comprises determining a dummy data cycle according to the parallel bit number, wherein each sub-data set includes at least one of the determined dummy data cycle.

24. The method of claim 23, wherein the dummy data cycle includes at least one data bit, the data bit of the dummy data cycle is set to be null.

25. The method of claim 23, further comprising:

comparing the output data and data sent back by the peripheral device after receiving the output data; and

configuring the dummy data cycle according to a comparison result.

26. The method of claim 16, wherein determining the parallel bit number further comprises:

sending a negotiation signal to the peripheral device to inform the peripheral device of the parallel bit number; and

transferring the output data to the peripheral device after receiving an acknowledge signal sent back from the peripheral device, wherein the acknowledge signal is to inform the optical storage system the peripheral device is ready to receive the output data.

27. The method of claim 26, wherein generating the output data further comprises dividing the output data into a plurality of sets of sub-data according to the parallel bit number, the number of sets of sub-data being the same as the parallel bit number.

28. The method of claim 27, wherein transferring includes transferring the sets of sub-data in parallel.

29. The method of claim 28, wherein the output data is compatible with a serial peripheral interface (SPI) standard and the output data includes at least a command data, an address data, and a plurality of data blocks.

30. The method of claim 29, wherein generating the output data further comprises:

dividing the command data into a plurality of sub-command data;

dividing the address data into a plurality of sub-address data;

dividing the data blocks into a plurality of sub-data blocks; and

generating each sub-data set according to one of the sub-command data, one of the sub-address data, and at least one of the sub-data blocks.

31. The method of claim 16, further comprising:

receiving input data from the peripheral device, wherein a number of bits of the input data received in parallel is determined according to the parallel bit number; and

storing the input data.

32. The method of claim 16, wherein one of the peripheral devices to which the optical storage system can be coupled is a non-volatile memory.

33. The method of claim 16, wherein the optical storage system is a digital video disk(DVD) system.

34. The system of claim 16, wherein the optical storage system is a digital video compact disc (VCD) system.

35. An optical storage system, comprising:

a data read subsystem to read out data stored in an optical storage medium;

a data process subsystem to generate data information and address information according to the read out data;

a plurality of pins for coupling to a non-volatile memory; and

an interface controller to generate output data according to the address information and the data information and to transfer the output data to the non-volatile memory, wherein a number of bits of the output data being transferred in parallel is configurable according to a parallel bit number, and the data information and the address information are outputted via the same pins, the interface controller comprising;

an address decoder to decode and output the address information;

a control register to determine the peripheral device to which the output data is to be transferred according to the decoded address information, and to determine the parallel bit number according to the peripheral device to which the output data is to be transferred;

an output buffer to store the data information; and

an interface encoder to generate the output data according to the data information and the address information;

wherein the non-volatile memory comprises;

a memory cell array to store data; and

a memory interface controller to control the non-volatile memory.

36. The system of claim 35, wherein the memory interface controller further comprises:

an input buffer to store a first portion of the output data;

a shifter to receive a second portion of the output data;

a multiplexing device to merge the first and the second portions of the output data and to store the merged portion of the output data in the input buffer; and

an interface decoder to decode the output data after the entire output data is received and to control the non-volatile memory according to the output data.

37. The system of claim 35, wherein the memory interface controller sends an acknowledge signal to the optical storage system after receiving a negotiation signal sent by the optical storage system for informing the non-volatile memory of the parallel bit number, wherein the acknowledge signal is to inform the optical storage system that the non-volatile memory is ready to receive the output data and the optical storage system starts to transfer the output data after receiving the acknowledge signal.

38. The system of claim 35, wherein the memory cell array of the non-volatile memory further comprises a one-time-program portion to store a one time program (OTP).

39. The system of claim 35, wherein the non-volatile memory is a FLASH memory.