Dynamic command and/or address mirroring system and method for memory modules

• US 7,546,435 B2
• Filed: 02/13/2007
• Issued: 06/09/2009
• Est. Priority Date: 02/05/2004
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: LaBerge, Paul A.
• Primary Examiner(s): Sough; Hyung S
• Assistant Examiner(s): Doan; Duc T
• Application Number:
  US11/706,032
• Publication Number:
  US 20070143553A1
• Time in Patent Office: 847 Days
• Field of Search: None
• US Class Current: 711/167
• CPC Class Codes: G06F 12/0653 with centralised address assignment
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00

Abstract

A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The memory devices are mounted in mirrored configuration with mirrored terminals of memory devices on opposite surfaces being interconnected. A memory hub mounted on each module alters the configuration of address and/or command signals coupled to the memory devices depending upon whether the memory devices on the first surface of the substrate or the memory devices on the second surface of the substrate are being accessed. Alternatively, the configuration of the address and/or command signals coupled to mirrored memory devices may be altered by a register mounted on the substrate that is coupled to the memory devices or by a memory controller coupled directly to memory devices on one or more memory modules.

Claims

1. A memory module, comprising:

an insulative substrate;

first and second pluralities of memory devices each having a plurality of terminals, each terminal of the memory devices of the first plurality corresponding to an identical memory device function as a correspondingly positioned terminal of the memory devices of the second plurality, the first plurality of memory devices being mounted to the insulative substrate having at least a portion of the terminals of the memory devices in the first plurality each interconnected to one of the terminals of one of the memory devices in the second plurality and having a different memory device function therefrom; and

a memory access device mounted on the substrate, the memory access device having a plurality of terminals that are coupled to respective ones of the interconnected terminals, the memory access device being operable to receive external memory requests and to couple address and control signals to the interconnected terminals responsive to the memory requests, at least one of the address signals or at least one of the control signals being dynamically coupled to the interconnected terminals in a first configuration if the first plurality of memory devices are being accessed, and the at least one of the address signals or at least one of the control signals being dynamically coupled to the interconnected terminals in a second configuration that is different from the first configuration if the memory devices of the second plurality are being accessed, the memory access device comprising;

a command queue that is operable to receive the memory requests, the memory queue further being operable to convert the memory requests into respective sets of command and address signals and to output the command and address signals in the order that the respective memory requests were received;

a command scheduler coupled to the command queue to receive the command and address signals from the command queue, the command scheduler arranging the timing of the command and address signals;

a micro command shifter coupled to receive the command and address signals from the command scheduler after the timing of the command and address signals have been arranged, the micro command shifter being operable to output the command and address signals in synchronism with the operation of the memory devices; and

a multiplexer coupled to the micro command shifter to receive the command signals or the address signals from the micro command shifter, the multiplexer being operable to arrange the command or address signals in either the first configuration or the second configuration depending on whether the memory devices of the first or second plurality are being accessed, the multiplexer being operable to couple the command or address signals in either the first configuration or the second configuration to the interconnected terminals.

2. The memory module of claim 1, wherein the first and second pluralities of memory devices are mounted on opposite sides of the insulative substrate.

3. The memory module of claim 1, wherein the memory access device is centrally positioned on the insulative substrate, and wherein the memory devices of the first and second pluralities are positioned to both sides of the memory access device, the memory access device being operable to couple respective sets of address or control signals in the first or second configuration to the memory devices of the first and second plurality on each side of the memory access device.

4. The memory module of claim 1, wherein a portion of the terminals of the memory devices of the first plurality are data terminals and are interconnected to data terminals of the memory devices of the second plurality, the memory access device structured to couple data signals to the interconnected data terminals irrespective of whether the first or second pluralities are being accessed.

5. The memory module of claim 1, wherein the multiplexer has first and second inputs, the first input being coupled to the micro command shifter and the second input being coupled to the command queue, the multiplexer being operable to receive command and address signals from the second input following a period of latency and to thereafter receive command and address signals from the first input.

6. The memory module of claim 1, further comprising a ring buffer coupled between the multiplexer and the memory devices.

7. The memory module of claim 1 wherein the memory access device comprises a register that is structured to receive and store address and control signals forming each of the memory requests, and couple the stored address and control signals to the memory devices.

8. The memory module of claim 1 wherein the memory devices each comprise a dynamic random access memory device.

9. A processor-based system, comprising:

a processor having a processor bus;

a system controller coupled to the processor bus, the system controller having a peripheral device port, the system controller further comprising a memory controller coupled to a system memory port;

at least one input device coupled to the peripheral device port of the system controller;

at least one output device coupled to the peripheral device port of the system controller;

at least one data storage device coupled to the peripheral device port of the system controller; and

a memory module coupled to the system memory port of the system controller, the memory module comprising;

an insulative substrate;

first and second pluralities of memory devices each having a plurality of terminals, each terminal of the memory devices of the first plurality corresponding to an identical memory device function as a correspondingly positioned terminal of the memory devices of the second plurality, the first plurality of memory devices being mounted to the insulative substrate having at least a portion of the terminals of the memory devices in the first plurality each interconnected to one of the terminals of one of the memory devices in the second plurality and having a different memory device function therefrom; and

a memory hub mounted on and centrally positioned on the insulative substrate, the memory hub having a plurality of terminals that are coupled to respective ones of the interconnected terminals, the memory hub being coupled to the system controller and operable to receive higher level memory requests from the memory controller and to couple address and control signals to the interconnected terminals of the memory devices on each side of the memory hub responsive to the memory requests, at least one of the address signals or at least one of the control signals being dynamically coupled to the interconnected terminals in a first configuration if the first plurality of memory devices are being accessed, and the at least one of the address signals or at least one of the control signals being dynamically coupled to the interconnected terminals in a second configuration that is different from the first configuration if the memory devices of the second plurality are being accessed, the memory hub comprising;

a command queue that is operable to receive the memory requests, the memory queue further being operable to convert the memory requests into respective sets of command and address signals and to output the command and address signals in the order that the respective memory requests were received;

a command scheduler coupled to the command queue to receive the command and address signals from the command queue, the command scheduler arranging the timing of the command and address signals;

a micro command shifter coupled to receive the command and address signals from the command scheduler after the timing of the command and address signals have been arranged, the micro command shifter being operable to output the command and address signals in synchronism with the operation of the memory devices; and

a multiplexer coupled to the micro command shifter to receive the command signals or the address signals from the micro command shifter, the multiplexer being operable to arrange the command or address signals in either the first configuration or the second configuration depending on whether the memory devices on the first surface or the memory devices on the second surface are being accessed, the multiplexer being operable to couple the command or address signals in either the first configuration or the second configuration to the interconnected terminals.