Memory usable in cache mode or scratch pad mode to reduce the frequency of memory accesses

• US 7,546,437 B2
• Filed: 07/25/2005
• Issued: 06/09/2009
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Cabillic, Gilbert, Lesot, Jean-Philippe
• Primary Examiner(s): Thai; Tuan V.
• Application Number:
  US11/188,491
• Publication Number:
  US 20060026353A1
• Time in Patent Office: 1,415 Days
• Field of Search: 711/100, 711/117, 711/118, 711/119, 711/129, 711/132, 711/154, 711/173
• US Class Current: 711/173
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2212/6012 of operating mode, e.g. cache mode or local memory mode
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor adapted to couple to external memory. The processor comprises a controller and data storage (e.g., cache memory). The data storage is configurable to operate in either a cache policy mode in which a miss results in an access of the external memory or in a scratch pad policy mode in which a miss does not result in an access of the external memory. The data storage comprises a first portion and a second portion, and only one of the portions is active at a time. The non-active portion is unusable to store or retrieve data (e.g., Java local variables). When the active portion does not have sufficient capacity for additional data to be stored therein, the other portion becomes the active portion.

Claims

1. A processor adapted to couple to external memory, comprising:

a controller;

data storage operated by said controller, said data storage configurable to operate in either a cache policy mode in which a miss results in an access of the external memory or in a scratch pad policy mode in which a miss does not result in an access of the external memory;

wherein said data storage comprises a first portion and a second portion, and wherein only one of said portions is active at a time, the non-active portion being unusable; and

wherein, when the active portion does not have sufficient capacity for additional data to be stored therein, the other portion becomes the active portion.

2. The processor of claim 1 wherein, when said data storage has insufficient space to accept additional data, the controller cleans only one portion of the data storage, thereby copying valid contents of the data portion to the external memory.

3. The processor of claim 1 wherein said data storage changes from the scratch pad policy mode to the cache policy mode to cause data located in the external memory to be loaded back into the active portion on a cache miss.

4. The processor of claim 1 wherein said data storage changes from the cache policy mode to the scratch pad policy mode upon switching from one portion being the active portion to another portion being the active portion.

5. The processor of claim 1 wherein an oscillation occurs in which the two portions take turns being the active portion without needing to perform an access to external memory.

6. The processor of claim 1 wherein said data storage comprises cache memory.

7. The processor of claim 1 wherein said data storage is usable to store multiple sets of local variables, each set of local variables being associated with a specific executable software method.

8. The processor of claim 7 wherein, upon return from a first method to a second method and if the set of local variables associated with the second method are stored in the external memory, the controller causes the data storage to operate in the cache policy to thereby cause the set of local variables associated with the second method to be copied back into the active portion upon a miss that targets at least one local variable from among said set of local variables.

9. A system, comprising:

a communications transceiver;

a first memory;

a controller communicatively coupled to said communications transceiver and said memory; and

a second memory operated by said controller, said second memory configurable to operate in either a cache policy mode in which a miss results in an access of the first memory or in a scratch pad policy mode in which a miss does not result in an access of the first memory;

wherein said second memory comprises a first portion and a second portion, and wherein only one of said portions is active at a time, the non-active portion being unusable; and

wherein, when the active portion does not have sufficient capacity for additional data to be stored therein, the other portion becomes the active portion.

10. The system of claim 9 wherein, when said second memory has insufficient space to accept additional data, the controller cleans only one portion of the second memory, thereby copying valid contents of the data portion to the first memory.

11. The system of claim 9 wherein said second memory changes from the scratch pad policy mode to the cache policy mode to cause data located in the first memory to be loaded back into the active portion on a cache miss.

12. The system of claim 9 wherein said second memory changes from the cache policy mode to the scratch pad policy mode upon switching from one portion being the active portion to another portion being the active portion.

13. The system of claim 9 wherein an oscillation occurs in which the two portions take turns being the active portion without needing to perform an access to first memory.

14. The system of claim 9 wherein the system comprises a cellular telephone.

15. The system of claim 9 wherein said second memory comprises cache memory.

16. The system of claim 15 wherein the controller and second memory are included in a processor and the first memory comprises memory external to said processor.

17. The system of claim 9 wherein said second memory is usable to store multiple sets of local variables, each set of local variables being associated with a specific executable software method.

18. The system of claim 9 wherein, upon return from a first method to a second method and if the set of local variables associated with the second method are stored in the first memory, the controller causes the second memory to operate in the cache policy to thereby cause the set of local variables associated with the second method to be copied back into the active portion upon a miss that targets at least one local variable from among said set of local variables.

19. The system of claim 18 wherein the active portion is flushed to invalidate said active portion.

20. A method, comprising:

using only a first portion of a cache memory data array to store local variables until said first portion has insufficient capacity for storing additional local variables, said cache memory data array comprising the first portion and a second portion;

once the first portion has insufficient capacity for storing additional local variables, using only the second portion of the cache memory data to store said additional local variables and not using the first portion; and

when the second portion has insufficient capacity for storing additional local variables, copying the local variables from only the first portion to external memory.

21. The method of claim 20 further comprising selecting a policy for the cache memory data array based on whether a state of the cache memory data array, said policy being either a cache policy in which a miss results in an access of the external memory or in a scratch pad policy in which a miss does not result in an access of the external memory.

22. The method of claim 20 further comprising copying local variables from the external memory to only one of said first or second portions.