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Memory usable in cache mode or scratch pad mode to reduce the frequency of memory accesses

  • US 7,546,437 B2
  • Filed: 07/25/2005
  • Issued: 06/09/2009
  • Est. Priority Date: 07/27/2004
  • Status: Active Grant
First Claim
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1. A processor adapted to couple to external memory, comprising:

  • a controller;

    data storage operated by said controller, said data storage configurable to operate in either a cache policy mode in which a miss results in an access of the external memory or in a scratch pad policy mode in which a miss does not result in an access of the external memory;

    wherein said data storage comprises a first portion and a second portion, and wherein only one of said portions is active at a time, the non-active portion being unusable; and

    wherein, when the active portion does not have sufficient capacity for additional data to be stored therein, the other portion becomes the active portion.

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