Algorithm mapping, specialized instructions and architecture features for smart memory computing

• US 7,546,438 B2
• Filed: 07/05/2005
• Issued: 06/09/2009
• Est. Priority Date: 07/19/2001
• Status: Active Grant

• Current Assignee: Stripe, Inc.
• Original Assignee: Shine C. Chung
• Inventors: Chung, Shine C.
• Primary Examiner(s): PATEL, HETUL B
• Application Number:
  US11/175,559
• Publication Number:
  US 20050246698A1
• Time in Patent Office: 1,435 Days
• Field of Search: 717/109, 717/149, 711/202
• US Class Current: 711/202
• CPC Class Codes: G06F 15/7821 Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G06Q 20/3576 Multiple memory zones on card
• CPC Class Codes: G07F 7/084 Additional components relating to data transfer and storing, e.g. error detection, self-diagnosis
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
• CPC Class Codes: H04Q 2213/13076 Distributing frame, MDF, cross-connect switch
• CPC Class Codes: H04Q 2213/13322 Integrated circuits
• CPC Class Codes: H04Q 3/0004 using crossbar selectors in the switching stages

Abstract

A smart memory computing system that uses smart memory for massive data storage as well as for massive parallel execution is disclosed. The data stored in the smart memory can be accessed just like the conventional main memory, but the smart memory also has many execution units to process data in situ. The smart memory computing system offers improved performance and reduced costs for those programs having massive data-level parallelism. This smart memory computing system is able to take advantage of data-level parallelism to improve execution speed by, for example, use of inventive aspects such as algorithm mapping, compiler techniques, architecture features, and specialized instruction sets.

Claims

1. A smart memory computing system, comprising:

a user space wherein data within has data-level parallelism;

a smart memory having multiple execution units wherein data can be processed in parallel and in situ;

a graphical representation describing data in said user space and interactions therewith; and

a compiler mapping data from said user space to said smart memory space and generating executable codes in accordance with said graphical representation,

wherein said graphical representation comprises;

objects containing said data within the said user space;

object boundary conditions containing boundaries between objects or between objects and a boundary of said user space; and

equations governing interactions between said data within the said user space, and

wherein said boundary conditions are specified as fixed values for variables, fixed values for derivatives of variables, equations containing arithmetic expressions of the variables and their derivatives, or combinations of the above.

2. A smart memory computing system, comprising:

a user space wherein data within has data-level parallelism;

a smart memory having multiple execution units wherein data can be processed in parallel and in situ;

a graphical representation describing data in said user space and interactions therewith; and

a compiler mapping data from said user space to said smart memory space and generating executable codes in accordance with said graphical representation,

wherein said graphical representation comprises;

objects containing said data within the said user space;

objects boundary conditions containing boundaries between objects or between objects and a boundary of said user space; and

equations governing interactions between said data within the said user space, and

wherein said compiler generates codes for said parallel processing based on;

accepting outputs from said graphical representation to obtain said objects, said boundary conditions, and said equations;

mapping data within said user space to the data within said smart memory space; and

applying a parallel instruction set to processing data within the said smart memory space.

3. The smart memory computing system as recited in claim 2, wherein said mapping preserves the physical location of the data in said user space to said data in the said smart memory space.

4. The smart memory computing system as recited in claim 2, wherein said parallel instruction set allows a single instruction code to be applied to P processors for processing data in the said smart memory space in parallel, wherein said P processors are indexed numerically.

5. The smart memory computing system as recited in claim 4, wherein said instruction code comprises fields of input operands from a multiple-port register file associated with each said processors, wherein said register files are indexed numerically.

6. The smart memory computing system as recited in claim 4, wherein said instruction code comprises fields of input operands from a common multiple-port register file not associated with any said P processors.

7. The smart memory computing system as recited in claim 4, wherein said instruction code comprises fields of input operands from processor-associated multiple-port register files, wherein said register files are indexed with a fixed offset to said processors.

8. The smart memory computing system as recited in claim 4, wherein said instruction code comprises fields of input operands from processor-associated multiple-port register files, wherein said register files are indexed in circular to said processors.

9. The smart memory computing system as recited in claim 4, wherein said instruction code comprises fields of input operands from processor-associated multiple-port register files, wherein said register files are input from all P processors to generate a single result.