Selecting test circuitry from header signals on power lead

• US 7,546,501 B2
• Filed: 09/12/2007
• Issued: 06/09/2009
• Est. Priority Date: 09/13/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US11/854,327
• Publication Number:
  US 20080065934A1
• Time in Patent Office: 636 Days
• Field of Search: 714/724, 714/726, 714/727, 714/733
• US Class Current: 714/726
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/31722 Addressing or selecting of test units, e.g. transmission protocols for selecting test units for scan test G01R31/318558
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G01R 31/31917 Stimuli generation or application of test patterns to the device under test [DUT]
• CPC Class Codes: G01R 31/31919 Storing and outputting test patterns G01R31/31924 takes precedence; arithmetic and random test patterns generator

Abstract

The present disclosure describes a novel method and apparatus for using a device'"'"'s power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals.

Claims

1. A process of testing an integrated circuit having functional circuitry and test circuitry connected to the functional circuitry, the test circuitry having test input leads receiving test signals for testing the functional circuitry and, the integrated circuit having power and ground leads, comprising:

A. receiving on a power lead of the integrated circuit message header signals that include start signals and command signals;

B. demodulating the message header signals;

C. recognizing the start and command signals of the demodulated message header signals; and

D. selecting the test input leads for receiving test signals in response to the command signals.

2. The process of claim 1 in which the selecting includes selecting internal scan test circuitry.

3. The process of claim 1 in which the selecting includes selecting boundary scan test circuitry.

4. The process of claim 1 in which the selecting includes selecting built in self test circuitry.

5. The process of claim 1 in which the selecting includes selecting built in test circuitry.

6. The process of claim 1 in which the selecting includes selecting functional test circuitry.

7. The process of claim 1 in which the receiving includes receiving direct current power for the functional circuitry and test circuitry on the power lead simultaneous with receiving the message header signals.

8. The process of claim 1 in which the receiving includes receiving direct current power for the functional circuitry and test circuitry on the power lead simultaneous with receiving the message header signals, and including filtering the message header signals from the direct current power prior to applying the direct current power to the functional circuitry and the test circuitry.

9. The process of claim 1 in which the selecting includes selecting debug circuitry.