Low power electrically alterable nonvolatile memory cells and arrays

• US 7,547,601 B2
• Filed: 10/30/2007
• Issued: 06/16/2009
• Est. Priority Date: 06/28/2005
• Status: Expired due to Fees

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Wang, Chih-Hsin
• Primary Examiner(s): Nguyen; Dao H
• Application Number:
  US11/978,875
• Publication Number:
  US 20080061321A1
• Time in Patent Office: 595 Days
• Field of Search: 438/257, 438/259, 438/261, 257/315, 257/316, 257/324
• US Class Current: 438/257
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of providing a memory cell includes providing a body of a semiconductor material having a first conductivity type, arranging a filter of a conductor-filter system in contact with a first conductor of the conductor-filter system, arranging at least portion of a second conductor of a conductor-insulator system in contact with the filter, arranging a first insulator of the conductor-insulator system in contact with the second conductor at an interface, arranging a first region spaced from the second conductor, arranging a channel of the body between the first region and the second conductor, arranging a second insulator adjacent to the first region, arranging a charge storage region between the first and the second insulators, arranging a first portion of a word-line adjacent to and insulated from the charge storage region, and arranging a second portion of the word-line adjacent to and insulated from the body.

Claims

1. A method of providing a memory cell, comprising:

providing a body of a semiconductor material having a first conductivity type;

arranging a filter of a conductor-filter system in contact with a first conductor of the conductor-filter system;

arranging at least portion of a second conductor of a conductor-insulator system including a drain in contact with the filter;

arranging a first insulator of the conductor-insulator system in contact with the second conductor at an interface;

arranging a first region spaced from the second conductor;

arranging a channel of the body between the first region and the second conductor;

arranging a second insulator adjacent to the first region;

arranging a charge storage region between the first and the second insulators;

arranging a first portion of a word-line adjacent to and insulated from the charge storage region; and

arranging a second portion of the word-line adjacent to and insulated from the body.

2. The method of claim 1, further comprising:

arranging a first dielectric of the filter adjacent to the first conductor; and

arranging a second dielectric of the filter adjacent to the first dielectric, wherein at least one of;

the second dielectric has a dielectric constant that is substantially greater than a dielectric constant of the first dielectric; and

the first dielectric has a first dielectric constant and a first thickness and the second dielectric has a second dielectric constant and a second thickness, and wherein a product of the second dielectric constant and the first thickness is substantially greater than a product of the first dielectric constant and the second thickness.

3. The method of claim 1, further comprising:

arranging a first dielectric of the filter adjacent to the first conductor, the first dielectric having an energy band gap; and

arranging a second dielectric adjacent to the first dielectric,

wherein the second dielectric has an energy band gap narrower than the energy band gap of the first dielectric.

4. The method of claim 3, wherein the first dielectric comprises oxide, and the second dielectric comprises material selected from the group consisting of nitride, oxynitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

5. The method of claim 3, wherein the first dielectric comprises oxynitride, and the second dielectric comprises material selected from the group consisting of nitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

6. The method of claim 1, further comprising selecting a work function of the charge storage region to be greater than a work-function of the second conductor.

7. The method of claim 1, wherein the charge storage region comprises p-type polysilicon, and the second conductor comprises n-type silicon.

8. The method of claim 1, wherein the first region and the second conductor comprise a semiconductor material having a second conductivity type.

9. The method of claim 1, wherein the body comprises silicon, and wherein the first region and the second conductor comprises a semiconductor material selected from the group consisting of silicon and SiGe.

10. The method of claim 1, wherein the first region comprises a first connector and a first junction, and the second conductor comprises a second connector and a second junction.

11. The method of claim 10, further comprising self-aligning at least one of:

the first connector and the first junction, and

the second connector and the second junction.

12. The method of claim 10, further comprising selecting at least one of the first and second junctions from the group consisting of p-n junction and Schottky junction.

13. The method of claim 10, wherein at least one of the first and second connectors comprises a material selected from the group consisting of polysilicon, poly-SiGe, SiGe, Al, Pt, Au, W, Mo, Ru, Ta, Ni, TaN, TiN, platinum-silicide, titanium suicide, tungsten-silicide, tungsten-polycide, nickel-silicide, cobalt-silicide, erbium suicide, terbium suicide, dysprosium suicide, and ytterbium suicide.

14. The method of claim 1, wherein the word-line comprises a material selected from the group consisting of n+ polysilicon, p+ polysilicon, poly-SiGe, Al, Pt, Au, W, Mo, Ru, Ta, Ni, TaN, TiN, and alloy formed thereof.

15. The method of claim 1, further comprising arranging a buried well of a semiconductor material having a second conductivity type between the body and a substrate.

16. The method of claim 1, wherein the first and the second insulators comprise dielectrics of an oxynitride system SiO_xN_1-x.

17. The method of claim 1, further comprising:

providing a plurality of the memory cells;

arranging the plurality of memory cells in a rectangular array of rows and columns;

arranging a plurality of the word-lines oriented in a first direction;

arranging a plurality of source-lines oriented in a second direction; and

arranging a plurality of bit-lines oriented in the second direction, wherein each of the word-lines connects a third conductor of each of the memory cells in a same row, each of the bit-lines connects the second conductor of each of the memory cells in a same column, and each of the source-lines connects the first region of each of the memory cells in a same column.

18. The method of claim 1 further comprising:

providing a plurality of the memory cells;

arranging the memory cells as pairs of memory cells; and

sharing a single first region between each of the memory cell pairs.

19. The method of claim 1, further comprising:

providing a plurality of the memory cells; and

arranging the memory cells as pairs of memory cells,

wherein one cell of one cell pair in one column and one cell of another cell pair in a same row and in an adjacent column shares a single first conductor therebetween.

20. The method of claim 1, wherein said first insulator and said second insulator are arranged between said drain and said first region.

21. The method of claim 20, wherein said first region includes a source.

22. The method of claim 1, wherein said filter comprises a first dielectric and a second dielectric.

23. The method of claim 22, wherein said first dielectric includes a tunneling dielectric and said second dielectric includes a blocking dielectric.

24. The method of claim 1, wherein said filter comprises a first material and said first insulator comprises a second material that is different than said first material.

25. The method of claim 1, wherein said filter comprises a first dielectric and said first insulator and said second insulator comprise a second dielectric that is different than said first dielectric.

26. The method of claim 1, wherein said filter is arranged between said first conductor and said drain.

27. The method of claim 1, wherein said charge storage region is arranged between said drain and a source.

28. A method of providing a memory cell, comprising:

providing a body of a semiconductor material having a first conductivity type;

arranging a filter of a conductor-filter system in contact with a first conductor of the conductor-filter system;

arranging at least portion of a second conductor of a conductor-insulator system in contact with the filter;

arranging a first insulator of the conductor-insulator system in contact with the second conductor at an interface;

arranging a first region spaced from the second conductor;

arranging a channel of the body between the first region and the second conductor;

arranging a second insulator adjacent to the first region;

arranging a charge storage region between the first and the second insulators;

arranging a first portion of a word-line adjacent to and insulated from the charge storage region;

arranging a second portion of the word-line adjacent to and insulated from the body; and

controlling flow of charge carriers of one polarity through the filter in one direction using a first set of electrically alterable potential barriers of the filter.

29. The method of claim 28, further comprising controlling flow of charge carriers of an opposite polarity through the filter in another direction that is substantially opposite to the one direction using a second set of electrically alterable potential barriers.

30. The method of claim 28, further comprising receiving energized charge carriers in the second conductor from the filter.

31. The method of claim 30, further comprising providing electrically alterable Image-Force potential barriers adjacent to the interface using the first insulator.

32. The method of claim 31, further comprising transporting the energized charge carriers over the Image-Force potential barrier onto the charge storage region.

33. The method of claim 32, wherein the transporting comprises at least one of:

using ballistic-hole injection, wherein the energized charge carriers comprise ballistic light-holes; and

using ballistic-electron injection, wherein the energized charge carriers comprise ballistic electrons.

34. The method of claim 28, wherein said first set of electrically alterable potential barriers comprise a first dielectric and a second dielectric.

35. The method of claim 28, further comprising applying an electric field to alter a height of at least one of said electrically alterable potential barriers.

36. A method of providing a memory cell, comprising:

providing a body of a semiconductor material having a first conductivity type;

arranging a filter of a conductor-filter system that includes a plurality of barriers and that is in contact with a first conductor of the conductor-filter system;

arranging at least portion of a second conductor of a conductor-insulator system in contact with the filter;

arranging a first insulator of the conductor-insulator system in contact with the second conductor at an interface;

arranging a first region spaced from the second conductor;

arranging a channel of the body between the first region and the second conductor;

arranging a second insulator adjacent to the first region;

arranging a charge storage region between the first and the second insulators;

arranging a first portion of a word-line adjacent to and insulated from the charge storage region; and

arranging a second portion of the word-line adjacent to and insulated from the body.