Methods for patterning a semiconductor film

• US 7,547,637 B2
• Filed: 06/21/2005
• Issued: 06/16/2009
• Est. Priority Date: 06/21/2005
• Status: Expired due to Fees

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Chau, Robert S., Kavalieros, Jack, Doyle, Brian S., Brask, Justin K., Majumdar, Amlan, Datta, Suman
• Primary Examiner(s): Jackson, Jr.; Jerome
• Assistant Examiner(s): Ho; Anthony
• Application Number:
  US11/158,661
• Publication Number:
  US 20070001173A1
• Time in Patent Office: 1,456 Days
• Field of Search: 257/66, 438/149, 438/151, 438/157, 438/166
• US Class Current: 438/717
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/30617 Anisotropic liquid etching
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

Claims

1. A method of patterning a monocrystalline silicon film comprising:

forming a hard mask on a monocrystalline silicon film;

etching said monocrystalline silicon film in alignment with said hard mask to form a monocrystalline silicon structure with a top surface and a pair of laterally opposite sidewalls, said monocrystalline silicon structure covered with said hard mask; and

exposing, to etch away a portion of said monocrystalline silicon structure, said monocrystalline silicon structure covered with said hard mask to a wet chemical etchant comprising water and less than 1% by volume NH₄OH, wherein said wet chemical etchant is self-limiting so that it stops on the first total intact <

111>

crystalline plane of said monocrystalline silicon structure.

2. The method of claim 1 wherein said monocrystalline silicon film has a (100) global crystal orientation.

3. The method of claim 2, wherein after etching to form said monocrystalline silicon structure covered with said hard mask, said sidewalls are aligned with a <

110>

plane.

4. The method of claim 1, further comprising:

after exposing said monocrystalline silicon structure to said wet chemical etchant, forming a gate dielectric and a gate electrode above said top surface of said monocrystalline silicon structure and on said sidewalls of said monocrystalline silicon structure.

5. The method of claim 4, further comprising:

removing said hard mask prior to forming said gate dielectric and gate electrode.

6. The method of claim 4, further comprising:

forming a source region and drain region in said monocrystalline silicon structure on opposite sides of said gate electrode.

7. The method of claim 1, wherein said wet chemical etchant has a chemical strength sufficient to etch <

100> and

<

110>

planes but insufficient chemical strength to etch <

111>

planes.

8. The method of claim 1, wherein the NH₄OH concentration is between 0.2-1% by volume and said wet chemical etchant has a temperature between 5-25°

C.