Semiconductor structures and memory device constructions
First Claim
1. An integrated circuit transistor comprising:
- a semiconductor structure including a pair of pillars and a connecting portion therebetween, the pillars having a bottom portion and a top portion, and having inner surfaces that face each other and outer surfaces that do not face each other, wherein the pillar top portions comprise heavily doped semiconductor material;
a dielectric material formed over at least a portion of the semiconductor structure;
a gate material formed on the dielectric material and positioned adjacent to at least some of the outer surfaces of the pillars; and
a channel extending between and forming an electrical connection between the bottom portions of the pair of pillars.
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Accused Products
Abstract
The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the source/drain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions.
72 Citations
8 Claims
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1. An integrated circuit transistor comprising:
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a semiconductor structure including a pair of pillars and a connecting portion therebetween, the pillars having a bottom portion and a top portion, and having inner surfaces that face each other and outer surfaces that do not face each other, wherein the pillar top portions comprise heavily doped semiconductor material; a dielectric material formed over at least a portion of the semiconductor structure; a gate material formed on the dielectric material and positioned adjacent to at least some of the outer surfaces of the pillars; and a channel extending between and forming an electrical connection between the bottom portions of the pair of pillars. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification