Random access of user design states in a configurable IC

• US 7,548,085 B2
• Filed: 03/13/2006
• Issued: 06/16/2009
• Est. Priority Date: 07/15/2005
• Status: Expired due to Fees

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Hutchings, Brad, Teig, Steven, Schmit, Herman, Redgrave, Jason
• Primary Examiner(s): Tran, Anh Q
• Application Number:
  US11/375,561
• Publication Number:
  US 20080272802A1
• Time in Patent Office: 1,191 Days
• Field of Search: 326 38- 41, 326/47
• US Class Current: 326/16
• CPC Class Codes: H03K 19/1731 Optimisation thereof
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Some embodiments of the invention is a configurable integrated circuit (IC) that includes (1) several configurable logic circuits, (2) a first routing network for connecting the configurable logic circuits, (3) several user design state (UDS) circuits, and (4) a second network communicatively coupled to the UDS circuits. In least one period during the operation of the IC, the second network receives addresses for a several UDS circuits in a random access manner. In some embodiments, the second network is a debug network for reading randomly state values stored by the addressed UDS circuits during the user-design operation of the IC.

Claims

1. An integrated circuit (“

IC”

) comprising;

a plurality of configurable logic circuits;

a first routing network for connecting the configurable logic circuits;

a plurality of user design state (“

UDS”

) circuits; and

a second debug network communicatively coupled to the UDS circuits, said second debug network for receiving addresses for a plurality of the UDS circuits in a random access manner and for randomly reading state values stored by the addressed UDS circuits during user-design operation of the IC;

wherein to read the plurality of UDS circuits, a plurality of read instructions are transmitted over the second debug network of the IC.

2. The IC of claim 1, wherein to address a particular set of UDS circuits, at least one address of the particular set of UDS circuits is transmitted over the debug network of the IC.

3. The IC of claim 1, wherein to read the plurality of UDS circuits, the read state values are read onto the second debug network.

4. The IC of claim 1, wherein the second debug network is further for randomly writing state values to the addressed UDS circuits.

6. The IC of claim 4, wherein to write to the plurality of UDS circuits, the written state values are written onto the second debug network.

15. The IC of claim 1, wherein said configurable logic circuits are for configurably performing a plurality of logic operations based on configuration data.

5. An integrated circuit (“

IC”

) comprising;

a plurality of configurable logic circuits;

a first routing network for connecting the configurable logic circuits;

a plurality of user design state (“

UDS”

) circuits; and

a second debug network communicatively coupled to the UDS circuits, said second debug network for receiving addresses for a plurality of the UDS circuits in a random access manner, and for randomly writing state values to the addressed UDS circuits,

wherein to write to the plurality of UDS circuits, a plurality of write instructions are transmitted over the second debug network of the IC.

7. A method of accessing an integrated circuit (“

IC”

) comprising a plurality of configurable circuits and a plurality of user design state (“

UDS”

) circuits, the method comprising;

while the IC is performing user-design operations, randomly addressing different UDS circuits through a first network connected to the UDS circuits, said first network separate from a second routing fabric network for connecting the configurable logic circuits of the IC; and

reading state values stored by the randomly addressed UDS circuits during the user-design operation of the IC;

wherein the UDS circuits are arranged in the IC according to a particular arrangement;

wherein randomly addressing different UDS circuits comprises successively accessing at least a plurality of the UDS circuits that are not aligned according to the particular arrangement.

8. The method of claim 7, wherein the particular arrangement is an array comprising rows and columns, and the UDS circuits are not aligned when the UDS circuits are not in the same row or the same column.

9. The method of claim 7, wherein the UDS circuits are grouped in tiles that are arranged according to the particular arrangement, wherein two UDS circuits are not aligned when the two UDS circuits are in two tiles that are not in the same row or the same column.

10. The method of claim 7, wherein addressing the plurality of UDS circuits comprises transmitting at least one address for the plurality of UDS circuits over the first network of the IC.

11. A method of accessing an integrated circuit (“

IC”

) comprising a plurality of configurable circuits and a plurality of user design state (“

UDS”

) circuits, the method comprising;

receiving, through a configuration network connected to the UDS circuits, addresses for different UDS circuits in a random access manner; and

writing state values stored by the randomly addressed UDS circuits;

wherein the UDS circuits are arranged in the IC according to a particular arrangement;

wherein randomly addressing different UDS circuits comprises successively accessing at least a plurality of the UDS circuits that are not aligned according to the particular arrangement.

12. The method of claim 11, wherein the particular arrangement is an array comprising rows and columns, and the UDS circuits are not aligned when the UDS circuits are not in the same row or the same column.

13. The method of claim 11, wherein the UDS circuits are grouped in tiles that are arranged according to the particular arrangement, wherein two UDS circuits are not aligned when the two UDS circuits are in two tiles that are not in the same row or the same column.

14. The method of claim 11, wherein addressing the plurality of UDS circuits comprises transmitting at least one address for the plurality of UDS circuits over the configuration network of the IC.