PLL with switched parameters

• US 7,548,122 B1
• Filed: 03/01/2006
• Issued: 06/16/2009
• Est. Priority Date: 03/01/2005
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Sequoia Communications Corporation
• Inventors: Groe, John B., Viani, Paul Lawrence
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US11/366,992
• Time in Patent Office: 1,203 Days
• Field of Search: 331/16, 331/34, 331/175, 331/17
• US Class Current: 331/16
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/1072 by changing characteristics of the charge pump, e.g. changing the gain
• CPC Class Codes: H03L 7/1075 by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth H03L7/1072 takes precedence
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A system and method of operating a phase-locked loop frequency synthesizer is disclosed herein. The disclosed method includes defining a first set of operating parameters applicable to operation of a phase-locked loop of the synthesizer in a first mode and defining a second set of operating parameters applicable to operation of the phase-locked loop in a second mode. A first detection signal is generated so as to initiate transition of the phase-locked loop into the second mode. The method further includes configuring, at least in part in response to the first detection signal, the phase-locked loop to operate in accordance with the second set of operating parameters.

Claims

1. A phase-locked loop frequency synthesizer comprising:

a phase-locked loop, including a charge pump and an integration filter, disposed to function in a first mode and in a second mode;

a mode detection circuit for generating a first detection signal to initiate transition of the phase-locked loop from the first mode to the second mode; and

a switching network for changing, at least in part in response to the first detection signal, the values of a first operating parameter and a second operating parameter of the phase-locked loop, said first operating parameter associated with the charge pump and said second operating parameter associated with the integration filter;

wherein a divider circuit comprises an N counter and the switching network switches the values of the operating parameters subsequent to generation of the first detection signal and upon the N counter registering a predefined count value.

2. The frequency synthesizer of claim 1 wherein the first mode corresponds to an acquisition mode of operation and the second mode corresponds to a track mode of operation.

3. The frequency synthesizer of claim 1 wherein the mode detection circuit is further operative to generate a second detection signal that changes the phase-locked loop into the second mode and wherein the switching network switches, in response to the second detection signal, the values of the first and second operating parameters from a first state to a second state.

4. The frequency synthesizer of claim 1 wherein the phased-lock loop includes:

a voltage-controlled oscillator for generating an output signal of a frequency determined by a control voltage;

a divider circuit for dividing the output signal to produce a frequency-divided signal; and

a phase/frequency detector disposed to compare phases between an input reference signal and the frequency-divided signal and to produce a first phase error signal and a second phase error signal;

wherein the charge pump circuit produces a charge pump signal in response to the first phase error signal and the second phase error signal and the integration filter produces the control voltage in response to the charge pump signal.

5. The frequency synthesizer of claim 4 wherein the mode detection circuit is connected to the phase/frequency detector and is responsive to the first phase error signal and the second phase error signal.

6. The frequency synthesizer of claim 5 wherein the mode detection circuit generates the first detection signal upon determining that a predefined number of sequential pulses of less than a minimum duration are included in the first phase error signal or the second phase error signal.

8. The frequency synthesizer of claim 4 wherein the mode detection circuit is responsive to the input reference signal and the frequency-divided signal.

24. The phase-locked loop of claim 1 wherein the first operating parameter is a charge pump current value and the second operating parameter is a loop filter component value.

25. The phase-locked loop of claim 1 wherein the loop filter component value is a resistor value.

7. A phase-locked loop frequency synthesizer comprising:

a phase-locked loop disposed to function in a first mode and in a second mode, said phase locked loop including;

a voltage-controlled oscillator for generating an output signal of a frequency determined by a control voltage;

a divider circuit for dividing the output signal to produce a frequency-divided signal;

a phase/frequency detector disposed to compare phases between an input reference signal and the frequency-divided signal and to produce a first phase error signal and a second phase error signal;

a charge pump circuit for producing a charge pump signal in response to the first phase error signal and the second phase error signal;

a loop filter which produces the control voltage in response to the charge pump signal;

a mode detection circuit for generating a first detection signal to initiate transition of the phase-locked loop from the first mode to the second mode; and

a switching network for changing, at least in part in response to the first detection signal values of one or more operating parameters of the phase-locked loop;

wherein the divider circuit comprises an N counter and the switching network switches the values of the operating parameters subsequent to generation of the first detection signal and upon the N counter registering a predefined count value.

9. A method of operating a phase-locked loop frequency synthesizer, the method comprising:

defining a first set of operating parameters applicable to operation of a phase-locked loop of the synthesizer in a first mode and a second set of operating parameters applicable to operation of the phase-locked loop in a second mode, said phase-locked loop having a charge pump and an integration filter and said first and said second set of operating parameters each including a first operating parameter associated with the charge pump and a second operating parameter associated with the integration filter;

generating a first detection signal so as to initiate transition of the phase-locked loop into the second mode; and

configuring, at least in part in response to the first detection signal, the phase-locked loop to operate in accordance with the second set of operating parameters, wherein said configuring includes switching the value of the second operating parameter of the second set of operating parameters;

wherein a divider circuit comprises an N counter and a switching network switches values of the operating parameters subsequent to generation of the first detection signal and upon the N counter registering a predefined count value.

10. The method of claim 9 wherein the first mode corresponds to an acquisition mode of operation and the second mode corresponds to a track mode of operation.

11. The method of claim 9 further including generating a second detection signal to transition the phase-locked loop into operation in the second mode and configuring, at least in part in response to the second detection signal, the phase-locked loop for operation in accordance with the second set of operating parameters.

12. The method of claim 9 wherein the phase-locked loop generates an output signal of a frequency determined by a control voltage, the method further including:

dividing the output signal to produce a frequency-divided signal;

comparing phases of an input reference signal and the frequency-divided signal and producing a first phase error signal and a second phase error signal;

producing a charge pump signal in response to the first phase error signal and the second phase error signal; and

generating the control voltage in response to the charge pump signal.

13. The method of claim 12 wherein the first detection signal is generated upon determining that at least a predefined number of pulses of less than a predefined duration are included in the first phase error signal or the second phase error signal.

26. The method of claim 9 wherein the first operating parameter is a charge pump current value and the second operating parameter is a loop filter component value.

27. The method of claim 26 wherein the loop filter component value is a resistor value.

14. A method of operating a phase-locked loop frequency synthesizer wherein the phase locked loop generates an output signal of a frequency determined by a control voltage, the method comprising:

defining a first set of operating parameters applicable to operation of a phase-locked loop of the synthesizer in a first mode and a second set of operating parameters applicable to operation of the phase-locked loop in a second mode;

generating a first detection signal so as to initiate transition of the phase-locked loop into the second mode; and

configuring, at least in part in response to the first detection signal, the phase-locked loop to operate in accordance with the second set of operating parameters;

wherein the phase-locked loop;

divides the output signal to produce a frequency-divided signal, the frequency divided signal being produced using an N counter;

compares phases of an input reference signal and the frequency-divided signal and producing a first phase error signal and a second phase error signal;

produces a charge pump signal in response to the first phase error signal and the second phase error signal; and

generates the control voltage in response to the charge pump signal; and

wherein the phase-locked loop is configured to operate in accordance with the second set of operating parameters subsequent to generation of the first detection signal and upon the N counter registering a predefined count value.

15. An apparatus for configuring operational parameters of a phase locked loop, comprising:

a mode detection circuit for generating a first detection signal to transition the phase-locked loop from a first operative mode to a second operative mode; and

a parameter switching network operative to switch, at least in part in response to the first detection signal, values of a first operating parameter associated with a charge pump and a second operating parameter associated with an integration filter of the phase-locked loop from a first state to a second state;

wherein a divider circuit comprises an N counter and the switching network switches the values of the operating parameters subsequent to generation of the first detection signal and upon the N counter registering a predefined count value.

16. The apparatus of claim 15 wherein the first operative mode corresponds to an acquisition mode of operation and the second operative mode corresponds to a track mode of operation.

17. The apparatus of claim 15 wherein the mode detection circuit is further operative to generate a second detection signal to transition the phase-locked loop into the second operative mode and wherein the parameter switching network is disposed to switch, at least part in response to the second detection signal, the values of the one or more operating parameters from the first state to the second state.

28. The apparatus of claim 15 wherein the first operating parameter is a charge pump current value and the second operating parameter is a loop filter component value.

29. The apparatus of claim 28 wherein the loop filter component value is a resistor value.

18. A phase-locked loop module, comprising:

a voltage-controlled oscillator for generating an output signal of a frequency determined by a control voltage;

a divider circuit for dividing the output signal to produce a frequency-divided signal;

a phase/frequency detector disposed to compare phases between an input reference signal and the frequency-divided signal and to produce a first phase error signal and a second phase error signal;

a charge pump circuit for producing a charge pump signal in response to the first phase error signal and the second phase error signal, the charge pump circuit characterized by a first operating parameter;

a loop filter for producing the control voltage in response to the charge pump signal, the loop filter characterized by a second operating parameter; and

a parameter switching arrangement for changing values of the first and second operating parameters subsequent to transition of the phase-locked loop from a first operative mode to a second operative mode;

wherein the divider circuit comprises an N counter and the switching arrangement switches the values of the operating parameters subsequent to generation of the first detection signal and upon the N counter registering a predefined count value.

19. The phase-locked loop module of claim 18 wherein the parameter switching arrangement includes a lock detection circuit for generating a lock detection signal to transition the phase-locked loop from the first operative mode to the second operative mode.

20. The phase-locked loop module of claim 18 wherein the first operative mode corresponds to an acquisition mode of operation and the second operative mode corresponds to a track mode of operation.

21. The phase-locked loop module of claim 19 wherein the lock detection circuit is further operative to generate an unlocked detection signal that prevents transition of the phase-locked loop to the second mode.

30. The module of claim 18 wherein the first operating parameter is a charge pump current value and the second operating parameter is a loop filter component value.

31. The module of claim 30 wherein the loop filter component value is a resistor value.

22. A phase-locked loop frequency synthesizer comprising:

a phase-locked loop disposed to function in a first operative mode and in a second operative mode;

a parameter switching arrangement for switching values of a first operating parameter of the phase-locked loop associated with a charge pump and a second operating parameter of the phase-locked loop associated with a loop filter of the phase-locked loop from a first state to a second state subsequent to transition of the phase-locked loop from the first operative mode into the second operative mode;

wherein a divider circuit comprises an N counter and the switching arrangement switches the values of the operating parameters subsequent to generation of the first detection signal and upon the N counter registering a predefined count value.

23. The phase-locked loop frequency synthesizer of claim 22 wherein the parameter switching arrangement includes a mode detection circuit for generating a first detection signal to initiate transition the phase-locked loop from the first operative mode to the second operative mode.

32. The synthesizer of claim 22 wherein the first operating parameter is a charge pump current value and the second operating parameter is a loop filter component value.

33. The synthesizer of claim 32 wherein the loop filter component value is a resistor value.