Buildup dielectric and metallization process and semiconductor package

• US 7,548,430 B1
• Filed: 08/01/2006
• Issued: 06/16/2009
• Est. Priority Date: 05/01/2002
• Status: Expired due to Fees

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Rusli, Sukianto, Hiner, David Jon, Huemoeller, Ronald Patrick
• Primary Examiner(s): Reichard; Dean A.
• Assistant Examiner(s): Semenenko; Yuriy
• Application Number:
  US11/497,617
• Time in Patent Office: 1,050 Days
• Field of Search: 361/765, 361/761, 361/736, 361/737, 361/739, 361/748, 361/749, 361/750, 361/751, 361/760, 174/520, 174/521, 174/262, 257/738, 257/759
• US Class Current: 361/760
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/92 Specific sequence of method steps
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/31 characterised by the arrangement or shape
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/50 : for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/30 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/91 : Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49789 : Obtaining plural product pieces from unitary workpiece

Abstract

A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.

Claims

1. A semiconductor package comprising:

a semiconductor die including bond pads;

a substrate, wherein the semiconductor die is mounted on a top surface of the substrate;

an encapsulation covering the semiconductor die and the top surface of the substrate;

blind vias formed through the encapsulation;

electrically conductive features disposed at the top surface of the encapsulation, the electrically conductive features being connected to the blind vias; and

a first buildup dielectric layer having an electrically conductive pattern formed therein, wherein the electrically conductive pattern is electrically connected to the electrically conductive features, wherein the electrically conductive pattern comprises electrically conductive traces extending entirely through the first buildup dielectric layer and extending in a direction substantially parallel to a top surface of the first buildup dielectric layer.

2. The semiconductor package of claim 1 wherein the first buildup dielectric layer is formed at least on the top surface of the encapsulation.

3. The semiconductor package of claim 2 wherein the encapsulation has sides and the first buildup dielectric layer has sides that are substantially coplanar with the sides of the encapsulation.

4. The semiconductor package of claim 2 wherein the first buildup dielectric layer entirely encloses the encapsulation.

5. The semiconductor package of claim 4 wherein the first buildup dielectric layer comprises sidewalls in contact with sides of the encapsulation.

6. The semiconductor package of claim 5 wherein the sidewalls contact the top surface of the substrate.

7. The semiconductor package of claim 1 wherein the electrically conductive pattern comprises electrically conductive vias formed within the first buildup dielectric layer and extending in a direction substantially perpendicular to the top surface of the first buildup dielectric layer.

8. A semiconductor package comprising:

a semiconductor die including bond pads;

a substrate, wherein the semiconductor die is mounted on a top surface of the substrate;

an encapsulation covering the semiconductor die and the top surface of the substrate;

blind vias formed through the encapsulation, wherein at least some of the blind vias extend to and contact the bond pads of the semiconductor die;

electrically conductive features disposed at the top surface of the encapsulation, the electrically conductive features being connected to the blind vias;

a first buildup dielectric layer having a first electrically conductive pattern formed therein, wherein the first electrically conductive pattern is electrically connected to the electrically conductive features; and

a second buildup dielectric layer having a second electrically conductive pattern formed therein, wherein the second electrically conductive pattern is electrically connected to the first electrically conductive pattern.

9. The semiconductor package of claim 8 wherein the first buildup dielectric layer is formed at least on the top surface of the encapsulation.

10. The semiconductor package of claim 9 wherein sides of the encapsulation, sides of the first buildup dielectric layer, and sides of the second buildup dielectric layer are substantially coplanar with one another.

11. The semiconductor package of claim 8 wherein the first buildup dielectric layer entirely encloses the encapsulation and wherein the second buildup dielectric layer entirely encloses the first buildup dielectric layer.

12. A semiconductor package comprising:

a semiconductor die including bond pads;

a substrate, wherein the semiconductor die is mounted on a top surface of the substrate;

an encapsulation covering the semiconductor die and the top surface of the substrate;

blind vias formed through the encapsulation;

electrically conductive features disposed at the top surface of the encapsulation, the electrically conductive features being connected to the blind vias;

a first buildup dielectric layer having a first electrically conductive pattern formed therein, wherein the first electrically conductive pattern is electrically connected to the electrically conductive features, wherein the first buildup dielectric layer entirely encloses the encapsulation, and wherein the first buildup dielectric layer comprises sidewalls in contact with sides of the encapsulation;

a second buildup dielectric layer having a second electrically conductive pattern formed therein, wherein the second electrically conductive pattern is electrically connected to the first electrically conductive pattern, wherein the second buildup dielectric layer entirely encloses the first buildup dielectric layer, and wherein the second buildup dielectric layer comprises sidewalls in contact with the sidewalls of the first buildup dielectric layer.

13. The semiconductor package of claim 12 wherein the sidewalls of the first buildup dielectric layer and the sidewalls of the second buildup dielectric layer contact the top surface of the substrate.

14. A semiconductor package comprising:

a semiconductor die mounted to a substrate;

wires electrically connecting the semiconductor die to a circuit pattern of the substrate;

an encapsulation encapsulating the semiconductor die, the substrate, and the wires;

laser-ablated via holes through the encapsulation;

vias formed by conductive material deposited within the laser-ablated via holes;

a first buildup dielectric layer formed on the encapsulation;

laser-ablated artifacts formed in the first buildup dielectric layer; and

a first electrically conductive pattern in the first buildup dielectric layer formed by filling the laser-ablated artifacts in the first buildup dielectric layer with a first metal layer.

15. The semiconductor package of claim 14 wherein the first electrically conductive pattern comprises copper.

16. The semiconductor package of claim 14 wherein the first electrically conductive pattern in the first buildup dielectric layer is electrically connected to the vias.

17. The semiconductor package of claim 14 further comprising:

a second buildup dielectric layer formed on the first buildup dielectric layer;

laser-ablated artifacts formed in the second buildup dielectric layer; and

a second electrically conductive pattern in the second buildup dielectric layer formed by filling the laser-ablated artifacts in the second buildup dielectric layer with a second metal layer.

18. The semiconductor package of claim 17 wherein the first buildup dielectric layer entirely encloses the encapsulation and wherein the second buildup dielectric layer entirely encloses the first buildup dielectric layer.

19. The semiconductor package of claim 14 further comprising:

a plurality of buildup dielectric layers;

laser-ablated artifacts in the plurality of buildup dielectric layers; and

electrically conductive patterns in the buildup dielectric layers formed by filling the laser-ablated artifacts in the buildup dielectric layers with metal layers.