Soft errors handling in EEPROM devices

• US 7,548,461 B2
• Filed: 06/22/2004
• Issued: 06/16/2009
• Est. Priority Date: 05/20/1992
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Mangan, John S., Mehrotra, Sanjay, Guterman, Daniel C., Craig, Jeffrey, Norman, Robert D., Auclair, Daniel L.
• Primary Examiner(s): DINH, SON T
• Application Number:
  US10/874,825
• Publication Number:
  US 20040237010A1
• Time in Patent Office: 1,820 Days
• Field of Search: 365/189.07, 365/185.2, 365/185.21, 365/185.22
• US Class Current: 365/185.22
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

Claims

1. A method of improving data retention in a nonvolatile writable memory having a plurality of storage elements each capable of storing at least a first and a second data state, where the memory uses a normal read value of a parameter for distinguishing between the first and the second data states, the method comprising:

reading a set of one or more storage elements using a first value of the parameter shifted from the normal read value;

determining whether the set of storage elements read correctly using the first value of the parameter; and

in response to storage elements not reading correctly using the first value of the parameter, correcting the data content of the set of data elements and rewriting the corrected data content back to the memory.

2. The method of claim 1, further comprising:

in response to storage elements reading correctly using the first value of the parameter,

reading the set of storage elements using a second value of the parameter shifted from the normal read value in a direction opposite that in which the first value is shifted relative to the normal read value;

determining whether the set of storage elements read correctly using the second value of the parameter; and

in response to storage elements not reading correctly using the second value of the parameter, correcting the data content of the set of data elements and rewriting the corrected data content back to the memory.

3. The method of claim 1, where the parameter is a voltage.

4. The method of claim 1, where the parameter is a current.

6. The method of claim 1, wherein the data content of the set of data storage elements is corrected using associated error correction code.

7. The method of claim 1, wherein said reading a set of one or more storage elements using the first value of the parameter, said determining whether the set of storage elements read correctly, and said correcting and rewriting the data content back to the memory are performed as part of a programming process.

9. The method of claim 1, wherein said reading a set of one or more storage elements using the first value of the parameter, said determining whether the set of storage elements read correctly, and said correcting and rewriting the data content back to the memory are performed as part of a read process.

5. The method of clam 1, wherein the corrected data content is rewritten back to the same set of data storage elements.

8. The method of clam 7, wherein the programming process writes data to storage elements other than those of the set of storage elements.

10. The method of clam 9, wherein the read process reads data from storage elements other than those of the set of storage elements.