Audio and video processing apparatus

• US 7,548,586 B1
• Filed: 02/03/2003
• Issued: 06/16/2009
• Est. Priority Date: 02/04/2002
• Status: Expired due to Fees

• Current Assignee: Tibet Mimar
• Original Assignee: Tibet Mimar
• Inventors: MIMAR, Tibet
• Primary Examiner(s): Senfi, Behrooz
• Application Number:
  US10/357,644
• Time in Patent Office: 2,325 Days
• Field of Search: 348/409, 348/420, 348/616, 348/384, 348/390, 348/401, 348/403, 348/411, 348/412, 348/413, 348/415, 348/416, 348/405, 348/402, 382/275, 382/251, 382/254, 375/240.27, 375/240.29, 375/240.12, 375/240.1, 375/240, 375/240.24, 700/19, 700/10, 700/20, 700/17, 700/83
• US Class Current: 375/240.26
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: H04N 21/42607 for processing the incoming bitstream

Abstract

A media processor for performing audio, video, and system layer tasks on a fully programmable single-chip integrated processor chip. The present invention performs video compression/decompression, audio compression/decompression, video input and output scaling, video input and output processing for enhancement, and system layer functions. The media processor is a single IC semiconductor chip that is coupled to one or more memory chips, audio front-end chip, and optional I/O interface chips. The media processor is compromised of the following integrated on a single IC semiconductor: Video processor with a SIMD vector engine, audio processor, stream processor, system (host) processor, and video scalers, LUTs and hardware blender.

Claims

1. A single semiconductor chip for performing audio, video, and system functions comprising:

a) a video processor comprising a RISC processor coupled to a single-instruction multiple data stream (SIMD) processor, which performs video compressing, video decompressing, video demodulating, and video enhancing;

wherein the programmable video processor further comprises means for performing fixed and variable size Discrete Cosine Transform (DCT), Inverse Discrete Cosine Transform (IDCT), motion estimation, motion compensation, forward quantization, inverse quantization, run-length encoding, run-length decoding, temporal interpolation of 2-dimensional blocks, spatial interpolation of 2-dimensional blocks, and block edge filtering for video standards MPEG-1, MPEG-2, MPEG-4 part 2, MPEG-4 part 10, RealNetworks video standard RealVideo-8, Microsoft Video standard Windows Media Player 8.0, H.263, and H.264; and

wherein the programmable video processor further comprises means for performing pre- and post-processing of video for enhancement purposes, using adaptive de-interlacing of video and adaptive motion compensation methods;

b) an audio processor for performing audio processing;

c) a digital bitstream processor which performs variable-length coding (VLC), variable-length decoding (VLD), multiplexing and demultiplexing of data streams, error correcting, decrypting, encrypting, and digital rights management processing;

d) a system processor for handling system and network connectivity functions, which performs TCP/IP stack, on-screen displays, web browser, teletext, and user interface functions;

e) a video scaler for scaling output video data with programmable parameters to match the resolution of a display unit;

f) a memory controller coupled to an external memory array, where said memory array stores video data, audio data, system data, on-screen display data, and instruction data for each of the system processor, the video processor, the audio processor, and the bitstream processor;

g) an audio input/output port coupled to the audio processor;

h) a plurality of video input/output ports coupled to the video processor;

i) a compressed audio/video input port coupled to the bitstream processor;

j) a user interface port coupled to the system processor;

k) a network interface port coupled to the system processor;

whereby said single semiconductor chip incorporates a plurality of Digital TV functions;

whereby said single semiconductor chip incorporates a plurality of Digital Camcorder functions; and

whereby said single semiconductor chip incorporates a plurality of Camera functions;

further comprising means for a plurality of DMA communications channels between the four processors (audio, video, system, and bitstream);

further comprising means for sharing one unified external memory by all processors for data and instruction memory, for buffering of intermediate results, and for inter-processing data and message passing;

further comprising means for buffering all input and output audio and video data in external unified memory;

further comprising means for passing data and communicating between processors using unidirectional packet based communication via circular queues in external unified memory;

the memory controller further comprising means for routing a plurality of communication packet means to a destination circular queue, said queue located in unified external memory; and

said packet means comprising coded information including data, identification of destination processor, identification of destination processor, identification of queue that is associated with destination processor, packet type, and packet size.

2. The single semiconductor chip of claim 1, the video processor further comprising means for blending of multiple video object planes and on-screen display.

3. The single semiconductor chip of claim 1, further comprising hardware video output port and video processor for blending of multiple video and on-screen display.

4. The single semiconductor chip of claim 1, further comprising means for performing Look-Up Table (LUT) based non-linear scaling of video output components, utilizing the programmable video processor.

5. The single semiconductor chip of claim 1, further comprising hardware Look-Up Tables (LUT) coupled to the video output port and said hardware Look-Up Tables also coupled to the video processor.

6. The single semiconductor chip of claim 1, the programmable audio processor further comprising means for performing audio data compression and decompression.

7. The single semiconductor chip of claim 1, the programmable audio processor further comprising means for performing voice recognition.

8. The single semiconductor chip of claim 1, the programmable audio processor further comprising means for performing acoustical echo cancellation.

9. The single semiconductor chip of claim 6, the programmable bitstream processor further comprising means for performing Huffman coding and arithmetic coding and decoding of video streams.

10. The single semiconductor chip of clam 9, the programmable stream processor further comprising means for performing multiplexing and demultiplexing of audio, video, and user data according to each of the audio/video streaming standards:

MPEG-1, MPEG-2, MPEG-4, ISMA 1.0, H.323.

11. The single semiconductor chip of claim 10, the programmable stream processor further comprising means for performing error correction, encryption and decryption.

12. The single semiconductor chip of claim 11 further comprising a hardware video scaler with programmable parameters coupled to the video processor, said hardware video scaler further comprising means for scaling video output data in two dimensions.

13. The single semiconductor chip of claim 12 further comprising a second hardware video scaler with programmable parameters coupled to the video processor, said second hardware scaler further comprising means for scaling a second video output to be displayed as a picture-in-picture.

14. The single semiconductor chip of claim 13, further comprising:

means for buffering video and audio input and output data utilizing FIFO means to decouple external video and audio timing from internal processing and to compensate for variable software latencies.

15. The single semiconductor chip of claim 14, wherein the video inputs coupled to the video processor connect directly to a camera sensor chip, a NTSC/PAL decoder, and a Terrestrial/Satellite tuner demodulator chip.

16. The single semiconductor chip of claim 15, wherein the video outputs coupled to video processor connect directly to a video back-end PAL/NTSC encoder, and said video outputs connect directly to a display of type LCD.

17. The single semiconductor chip of claim 16, wherein the video outputs coupled to video processor connect directly to a video back-end PAL/NTSC encoder, and said video outputs connect directly to a display of type plasma.

18. The single semiconductor chip of claim 17, wherein an interface hardware coupled to the video processor connects directly to a physical layer HDMI chip.

19. The single semiconductor chip of claim 18, wherein an interface hardware coupled to the video processor connects directly to a physical layer USB chip.

20. The single semiconductor chip of claim 19, wherein the IDE interface coupled to the system processor connects directly to a hard disk, a CD-RW disk drive, and a DVD disk drive.

21. The single semiconductor chip of clam 20, where the IIC interface coupled to the system processor provides a direct control interface for external chips that implement the IIC interface and protocol.

22. The single semiconductor chip of claim 21, wherein the IIS interface coupled to audio processor provides direct connection to audio front-end chips for multi channel audio input and output, where those audio front-end chips implement the IIS interface and protocol.

23. The single semiconductor chip of claim 22, the memory controller further comprising means for selectively performing, during a DMA transfer from external memory:

transferring a two-dimensional sub-block of an interlaced video field, and two-dimensional video sub-sampling.

24. The single semiconductor chip of claim 23, wherein the programmable video processor comprises a dual-issue processor including a standard RISC and a SIMD vector engine, whereby the RISC processor controls all data flow and data I/O including loading and storing of vector register elements.

25. The single semiconductor chip of claim 23, wherein the programmable video processor is a VLIW processor issuing two or more instructions per processor-clock cycle, and wherein one of the said issuing instructions is of SIMD type.

26. The single semiconductor chip of claim 23, the memory controller further comprising means for implementing a plurality of First-In-First-Out (FIFO) type circular queues in unified memory and maintaining buffer fullness information for each data channel that is readable by each of the four on-chip processors.

27. The signal semiconductor chip of claim 23, the bitstream processor further comprising a coprocessor for implementing encryption/decryption and DVD de-scrambler functions.

28. The single semiconductor chip of claim 27, the bitstream processor further comprising a hardware block for implementing encryption/decryption and DVD de-scrambler functions.