Method and system for performing crosstalk analysis

• US 7,549,134 B1
• Filed: 06/30/2006
• Issued: 06/16/2009
• Est. Priority Date: 08/30/2002
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Zhao, Hong, Chiu, Hsien-Yen, Spyrou, Athanasius, Li, Jun
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): BOWERS, BRANDON
• Application Number:
  US11/479,279
• Time in Patent Office: 1,082 Days
• Field of Search: 716 4- 6
• US Class Current: 716/115
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

Disclosed is an improved approach for performing crosstalk and signal integrity analysis in which multiple variables are taken into account when analyzing the effects of on-chip crosstalk, such as for example coupled wire length, ratio of coupling capacitance, and aggressor and victim driver types. Rather than performing a full-chip simulation, the potential crosstalk effects can be pre-characterized by performing simulation/modeling over specific net portions by systematically changing the values of these multiple variables. A set of patterns characterized from the variables are formed from the modeling. During the analysis process, the IC design is checked of the presence of the patterns, from which is produced the expected delay impact for crosstalk in the design.

Claims

1. A method for performing crosstalk analysis for the design of an integrated circuit, comprising:

characterizing a set of IC components based upon values of a plurality of variables comprising wirelength values, aggressor driver type values, victim driver type values, and ratio of coupling capacitance values;

identifying at least one of a set of patterns based at least in part upon the values of the plurality of variables;

analyzing an IC design to identify existence of any patterns from the set of patterns; and

determining delay impact of crosstalk based at least in part upon an act of identifying the existence of any patterns.

2. The method of claim 1 in which device-level simulation is performed for the act of characterizing the set of IC components.

3. The method of claim 2 in which approximately or at least 192 simulations per delay transition edge are performed.

4. The method of claim 2 in which the delay impact is evaluated against one or more of the plurality of variables to determine crosstalk impact.

5. The method of claim 4 in which asymptotic delay uncertainty is tracked as a function of coupled wire length against driver-normalized delay.

6. The method of claim 2 in which HSPICE is employed for the device-level simulation.

7. The method of claim 1 in which delay uncertainty is bounded with worst-case analysis.

8. The method of claim 1 in which the IC design in its entirety is analyzed for the existence of the patterns.

9. The method of claim 1 in which only specified portions of the IC design are analyzed for the existence of the patterns.

10. The method of claim 9 in which only wires having a given location, length, or specified characteristic are analyzed for the existence of any patterns.

11. The method of claim 1 in which the delay impact is determined based upon numerical models for delay developed from characterizing the set of IC components.

12. The method of claim 1, further comprising:

modifying the IC design if excessive crosstalk effects are identified.

13. The method of claim 12 in which a replace or insert methodology is applied to modify the IC design.

14. The method of claim 13 in which the replace or insert methodology comprises adding buffers, modifying driver strengths, and/or enhancing grid spacing.

15. A system for performing crosstalk analysis for the design of an integrated circuit, comprising:

means for characterizing a set of IC components based upon values of a plurality of variables comprising wirelength values, aggressor driver type values, victim driver type values, and ratio of coupling capacitance values;

means for identifying at least one of a set of patterns based at least in part upon the values of the plurality of variables;

means for analyzing an IC design to identify existence of any patterns from the set of patterns; and

means for determining delay impact of crosstalk based at least in part upon an act of identifying the existence of any patterns.

16. A computer program product comprising a computer usable medium having executable code to execute a process for performing crosstalk analysis for the design of an integrated circuit, the process comprising:

characterizing a set of IC components based upon values of a plurality of variables comprising wirelength values, aggressor driver type values, victim driver type values, and ratio of coupling capacitance values;

identifying at least one of a set of patterns based at least in part upon the values of the plurality of variables;

analyzing an IC design to identify existence of any patterns from the set of patterns; and

determining delay impact of crosstalk based at least in part upon an act of identifying the existence of patterns.