Nonplanar device with thinned lower body portion and method of fabrication

• US 7,550,333 B2
• Filed: 05/23/2006
• Issued: 06/23/2009
• Est. Priority Date: 10/25/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Chau, Robert S., Letson, Thomas A., Brask, Justin K., Doyle, Brian
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US11/440,313
• Publication Number:
  US 20060214231A1
• Time in Patent Office: 1,127 Days
• Field of Search: 438/157, 438/283, 438/284, 438/978, 257/E21.442
• US Class Current: 438/157
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence
• CPC Class Codes: H01L 2924/13067 FinFET, source/drain region shapes fins on the silicon surface
• CPC Class Codes: Y10S 438/978 forming tapered edges on substrate or adjacent layers

Abstract

A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Claims

1. A method of forming a device comprising:

forming a semiconductor body on an insulating layer of a substrate, said semiconductor body having a top surface opposite a bottom surface formed on said insulating layer and a pair of laterally opposite sidewalls wherein the laterally opposite sidewalls include a tapered portion such that the distance between said laterally opposite sidewalls is less at the bottom surface of said semiconductor body than at the top surface of said semiconductor body;

forming a gate dielectric layer on and in direct contact with said top surface of said semiconductor body and on said sidewalls of said semiconductor body, wherein the composition of said gate dielectric layer formed on said top surface is the same composition as said gate dielectric layer on said sidewalls;

forming a gate electrode on said gate dielectric layer on said top surface of said semiconductor body and adjacent to said gate dielectric layer on said sidewalls of said semiconductor body; and

forming a pair of source/drain regions in said semiconductor body on opposite sides of said gate electrode.

2. The method of claim 1 wherein the width at the bottom of said semiconductor body is approximately ½

to ⅔

of the width at the top of said semiconductor body.

3. The method of claim 1 wherein said distance between said sidewalls is uniform at the top portion of said semiconductor body and becomes increasingly smaller near the bottom portion of said semiconductor body.

4. The method of claim 1 wherein the distance between said sidewalls of said semiconductor body at the top surface is between 20-30 nm and wherein the distance between said laterally opposite sidewalls near the bottom is between 10-15 nm.

5. A method of forming a transistor comprising:

providing a substrate having an oxide insulating layer formed thereon and a semiconductor thin film formed on the oxide insulating layer;

etching said semiconductor film to form a semiconductor body having a top surface opposite a bottom surface on said oxide insulating film and a pair of laterally opposite sidewalls;

etching said semiconductor body to reduce the distance between laterally opposite sidewalls near the bottom of said semiconductor body relative to the top of said semiconductor body;

forming a gate dielectric layer on and in direct contact with the top surface and sidewalls of said semiconductor body, wherein the composition of said gate dielectric layer formed on said top surface is the same composition as said gate dielectric layer on said sidewalls;

forming a gate electrode on said gate dielectric layer on the top of said semiconductor body and adjacent to the gate dielectric layer on the sidewalls of said semiconductor body; and

forming a pair of source/drain regions in said semiconductor body on opposite sides of said gate electrode.

6. The method of claim 5 wherein said etching of said semiconductor film stops on said oxide insulating layer.

7. The method of claim 5 wherein said semiconductor body comprises silicon and wherein said etching of said semiconductor film is a dry etching process which utilizes a chemistry comprising HBr/O2.

8. The method of claim 5 wherein the etching of said semiconductor body reduces the distance between the laterally opposite sidewalls near the bottom portion of said semiconductor body without significantly etching the top portion of said semiconductor body.

9. The method of claim 8 wherein said semiconductor body is silicon and is etched by a dry etching process utilizing a chemistry comprising HBr/O₂.

10. The method of claim 8 wherein the power utilized during said etching of said semiconductor body to reduce the thickness of the bottom portion utilizes an RF bias between 50-70 watts.

11. The method of claim 8 wherein the etching process utilized to reduce the distance between the sidewalls on the bottom portion of said semiconductor body utilizes a total HBr/O₂ gas flow between 150-180 mL/min.

12. The method of claim 5 further comprising after etching said semiconductor body to reduce the distance between laterally opposite sidewalls of said semiconductor body near the bottom portion, exposing said semiconductor body to a wet chemistry comprising NH₄OH.

13. The method claim 5 wherein said etching of said semiconductor film to form said body utilizes a first process gas chemistry and a first RF bias and said etching of said semiconductor body to reduce the thickness of said bottom portion utilizes a second process gas and a second RF bias wherein said second RF bias is less than said first RF bias.

14. The method of claim 13 wherein said first process gas is the same as said second process gas.

15. The method of claim 14 wherein said first and second process gas comprises HBr/Ar/O₂.