Method and structure for forming strained SI for CMOS devices

• US 7,550,338 B2
• Filed: 09/13/2007
• Issued: 06/23/2009
• Est. Priority Date: 11/05/2003
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Haining S., Zhang, Ying, Steegen, An L.
• Primary Examiner(s): Smoot; Stephen W
• Application Number:
  US11/854,829
• Publication Number:
  US 20080003735A1
• Time in Patent Office: 649 Days
• Field of Search: 438/218
• US Class Current: 438/199
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02658 Pretreatments cleaning in general H01L21/02041
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI
• CPC Class Codes: H01L 29/7849 : the means being provided under the channel

Abstract

A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.

Claims

1. A method for manufacturing a device including an n-type device and a p-type device, comprising:

growing a first strain layer on a semiconductor substrate;

growing a silicon layer above the first strain layer;

forming a gap between the semiconductor substrate and the silicon layer by removing at least a portion of the silicon layer and the first strain layer from above the semiconductor substrate such that a portion of the silicon layer and a portion of the first strain layer remains above the gap;

growing a second strain layer in the gap; and

further comprising forming a spacer material on sidewalls of the semiconductor substrate, wherein the second strain layer is grown on at least a portion which is substantially directly under a channel of the n-type device.

2. A method for manufacturing a device including an n-type device and a p-type device, comprising:

growing a first strain layer on a semiconductor substrate;

growing a silicon layer above the first strain layer;

forming a gap between the semiconductor substrate and the silicon layer by removing at least a portion of the silicon layer and the first strain layer from above the semiconductor substrate such that a portion of the silicon layer and a portion of the first strain layer remains above the gap;

growing a second strain layer in the gap; and

further comprising forming a spacer material on sidewalls of the semiconductor substrate, wherein the second strain layer is grown on at least a portion which is substantially directly under at least one of a source region or drain region of the p-type device.

3. A method for manufacturing a device including an n-type device and a p-type device, comprising:

growing a first strain layer on a semiconductor substrate;

growing a silicon layer above the first strain layer;

forming a gap between the semiconductor substrate and the silicon layer by removing at least a portion of the silicon layer and the first strain layer from above the semiconductor substrate such that a portion of the silicon layer and a portion of the first strain layer remains above the gap;

growing a second strain layer in the gap;

before the gap is formed, forming trenches in the semiconductor substrate;

before the growing of the second strain layer, forming spacer material on sidewalls; and

after the spacer material is formed, removing the spacer material.

4. The method of claim 3, further comprising filling the trenches with an oxide material.