Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device

• US 7,550,396 B2
• Filed: 05/01/2007
• Issued: 06/23/2009
• Est. Priority Date: 09/29/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Mazur, Martin, Klais, Jochen, Richter, Ralf, Frohberg, Kai, Salz, Heike, Lehr, Matthias, Mueller, Sven, Hohage, Joerg, Schaller, Matthias, Grimm, Volker
• Primary Examiner(s): EVERHART, CARIDAD
• Application Number:
  US11/742,878
• Publication Number:
  US 20080081480A1
• Time in Patent Office: 784 Days
• Field of Search: 438/757, 438/703, 438/199, 438/231, 438/682, 438/740, 438/792, 257/E21.249, 257/E21.257, 257/E21.438, 257/E29.266, 257/E21.051
• US Class Current: 438/757
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.

Claims

1. A method, comprising:

forming a first stress-inducing layer above a first transistor and a second transistor, wherein forming said first stress-inducing layer comprises depositing a stressed material layer and forming an etch indicator layer thereon;

performing a plasma treatment on said first stress-inducing layer for densifying a surface thereof;

forming a first resist mask above said first stress-inducing layer having said densified surface to cover said first transistor, said first resist mask exposing a portion of said first stress-inducing layer; and

removing said exposed portion of said first stress-inducing layer from above said second transistor.

2. The method of claim 1, wherein said plasma treatment is performed in an oxidizing ambient.

3. The method of claim 1, wherein performing said plasma treatment and forming said first stress-inducing layer are performed in situ.

4. The method of claim 1, wherein said first stress-inducing layer comprises intrinsic compressive stress.

5. The method of claim 1, further comprising forming an etch stop layer on said first and second transistors prior to forming said first stress-inducing layer.

6. The method of claim 1, wherein said stressed material layer comprises silicon nitride.

7. The method of claim 6, wherein forming said first stress-inducing layer further comprises forming a cap layer on said etch indicator layer, said cap layer comprising silicon nitride.

8. The method of claim 1, further comprising forming a second stress-inducing layer above said first and second transistors and selectively removing said second stress-inducing layer from said first transistor on the basis of a second resist mask.

9. The method of claim 8, further comprising performing a plasma treatment for sealing a surface of said second stress-inducing layer prior to forming said second resist mask.

10. A method, comprising:

forming a silicon nitride containing material layer above a device area of a semiconductor device;

forming an etch indicator layer on said silicon nitride containing material layer;

performing a plasma treatment in an oxidizing ambient to modify a surface of said silicon nitride containing material layer;

forming a resist mask above said plasma treated silicon nitride containing material layer; and

performing an etch process on the basis of said resist mask.

11. The method of claim 10, wherein said silicon nitride containing material layer is a stress-inducing dielectric layer located above a transistor device.

12. The method of claim 10, wherein said silicon nitride containing material layer is used as an anti-reflective layer for forming said resist mask.

13. The method of claim 10, wherein forming said silicon nitride containing material layer comprises forming a silicon dioxide material as a cap layer of said silicon nitride containing material layer.

14. The method of claim 10, further comprising forming a cap layer on said silicon nitride containing material layer after performing said plasma treatment.

15. The method of claim 10, wherein forming said silicon nitride containing material layer comprises depositing a first silicon nitride material, depositing a silicon dioxide material on said silicon nitride and depositing a second silicon nitride material on said silicon dioxide material.

16. The method of claim 10, further comprising forming an etch stop layer on said device area of said semiconductor device prior to forming said silicon nitride containing material layer.

17. The method of claim 10, further comprising forming a dielectric material layer on said silicon nitride containing material layer and patterning said dielectric layer using said silicon nitride containing material layer as an etch stop layer.

18. The method of claim 17, wherein said dielectric layer comprises a low-k dielectric material.

19. A method, comprising:

forming a first stress-inducing layer having a first type of intrinsic stress above a first device region and a second device region, wherein forming said first stress-inducing layer comprises forming an etch indicator layer;

forming a first resist mask above said first stress-inducing layer, said first resist mask exposing said second device region and covering said first device region;

selectively removing said first stress-inducing layer from above said second device region;

forming a second stress-inducing layer having a second type of intrinsic stress above said first and second device regions;

forming a second resist mask above said second stress-inducing layer, said second resist mask exposing said first device region and covering said second device region; and

performing at least one plasma treatment at least prior to forming said second resist mask.

20. The method of claim 19, wherein forming said first stress-inducing layer further comprises forming a silicon nitride containing material layer and forming a cap on said silicon nitride containing material layer.

21. The method of claim 19, wherein forming said first stress-inducing layer comprises forming a first silicon nitride layer, forming said etch indicator layer thereon, said etch indicator layer having a different material composition compared to said first silicon nitride layer, and forming a second silicon nitride layer on said etch indicator layer.

22. The method of claim 19, further comprising forming an etch stop layer on said first and second device regions prior to forming said first stress-inducing layer.