Method and apparatus transporting charges in semiconductor device and semiconductor memory device

• US 7,550,800 B2
• Filed: 06/28/2005
• Issued: 06/23/2009
• Est. Priority Date: 06/06/2003
• Status: Expired due to Fees

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Wang, Chih-Hsin
• Primary Examiner(s): Nguyen; Dao H
• Application Number:
  US11/169,399
• Publication Number:
  US 20060001053A1
• Time in Patent Office: 1,456 Days
• Field of Search: 257/316, 257/324, 365/185.18
• US Class Current: 257/316
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A conductor-filter system, a conductor-insulator system, and a charge-injection system are provided. The conductor-filter system provides band-pass filtering function, charge-filtering function, voltage-divider function, and mass-filtering function to charge-carriers flows. The conductor-insulator system provides Image-Force barrier lowering effect to collect charge-carriers. The charge-injection system includes the conductor-filter system and the conductor-insulator system, wherein the filter of the conductor-filter system contacts the conductor of the conductor-insulator system. Method and apparatus on charges filtering, injection, and collection are provided for semiconductor device and nonvolatile memory device. Additionally, method and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided to the charge-injection system and devices operation. Memory cells and array architectures and manufacturing method thereof are provided.

Claims

1. A memory cell comprising:

a conductor-filter system including;

a first conductor for supplying thermal charge carriers; and

a filter contacting the first conductor and including dielectrics for providing a filtering function on charge carriers of one polarity, wherein the filter includes;

a first set of electrically alterable potential barriers for controlling flow of the charge carriers of one polarity through the filter in one direction, and

a second set of electrically alterable potential barriers for controlling flow of charge carriers of an opposite polarity through the filter in another direction that is substantially opposite to the one direction;

a conductor-insulator system including;

a second conductor contacting the filter and including energized charge carriers from the filter; and

an insulator contacting the second conductor at an interface and including an Image-Force potential barrier adjacent to the interface, wherein the Image-Force potential barrier is electrically alterable to permit the energized charge carriers transporting there over;

a body of a semi-conductor material having a first conductivity type;

first and second spaced-apart regions formed in the body and having a second conductivity type, with a channel of the body defined there between;

a channel dielectric adjacent to the channel; and

a charge storage region disposed in between the insulator and the channel dielectric.

2. The memory cell of claim 1, wherein the filter comprises:

a first dielectric disposed adjacent to the conductor and having an energy band gap; and

a second dielectric disposed adjacent to the first dielectric,

wherein the second dielectric has an energy band gap narrower than the energy band gap of the first dielectric.

3. The memory cell of claim 2, wherein the first dielectric has a first dielectric constant and the second dielectric has a dielectric constant that is substantially greater than the first dielectric constant.

4. The memory cell of claim 2, wherein the first dielectric has a first dielectric constant and a first thickness and the second dielectric has a second dielectric constant and a second thickness, and wherein a product of the second dielectric constant and the first thickness is substantially greater than a product of the first dielectric constant and the second thickness.

5. The memory cell of claim 2, wherein the first dielectric comprises oxide having a thickness in a range of about 1.5 nm to about 4 nm, and the second dielectric comprises material selected from the group consisting of nitride, oxynitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

6. The memory cell of claim 2, wherein the first dielectric comprises oxynitride having a thickness in a range of about 1.5 nm to about 4 nm, and the second dielectric comprises material selected from the group consisting of nitride Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

7. The memory cell of claim 1, wherein the charge storage region comprises polysilicon.

8. The memory cell of claim 1, wherein the charge storage region comprises a plurality of spaced-apart nano-particles.

9. The memory cell of claim 8, wherein the nano-particles comprise material selected from the group consisting of Si, Ge, SiGe alloy, H_fO₂, Au, Ag, and Pt.

10. The memory cell of claim 1, wherein the charge storage region comprises a dielectric including a plurality of trapping centers.

11. The memory cell of claim 1, wherein the energized charge carriers has an energy distribution with an energy spectrum in the range of about 30 meV to about 300 meV.

12. The memory cell of claim 1, wherein the energized charge carriers include light-holes.

13. The memory cell of claim 1, wherein the energized charge carriers include electrons.

14. The memory cell of claim 1, wherein the energized charge carriers include piezo-holes.

15. The memory cell of claim 1, wherein the energized charge carriers include piezo-electrons.

16. A memory cell comprising:

a first conductor-material system including;

a first conductor including thermal charge carriers with an energy distribution; and

a filter contacting the first conductor at a first interface and including dielectrics for providing a filtering function on charge carriers of one polarity, wherein the filter includes;

a first set of electrically alterable potential barriers for controlling flow of the charge carriers of one polarity through the filter in one direction, and

a second set of electrically alterable potential barriers for controlling flow of charge carriers of an opposite polarity to the one polarity through the filter in another direction that is substantially opposite to the one direction;

a second conductor-material system including;

a second conductor contacting the filter and including energized charge carriers with an energy distribution from the filter; and

an insulator contacting the second conductor at a second interface and including an electrically alterable Image-Force potential barrier adjacent to the second interface

a body of a semiconductor material including a first conductivity type;

first and second spaced-apart regions formed in the body and including a second conductivity type, with a channel of the body defined there between;

a channel dielectric adjacent to the channel; and

a charge storage region disposed in between the insulator and the channel dielectric for storing the energized charge carriers from the second conductor.

17. The memory cell of claim 16, wherein the filter comprises:

a first dielectric disposed adjacent to the first conductor and including an energy band gap; and

a second dielectric disposed adjacent to the first dielectric,

wherein the second dielectric has an energy band gap narrower than the energy band gap of the first dielectric.

18. The memory cell of claim 17, wherein the first dielectric has a first dielectric constant and a first thickness and the second dielectric has a second dielectric constant and a second thickness, and wherein a product of the second dielectric constant and the first thickness is substantially greater than a product of the first dielectric constant and the second thickness.

19. The memory cell of claim 16, wherein the charge storage region comprises polysilicon.

20. The memory cell of claim 16, wherein the charge storage region comprises a plurality of spaced-apart nano-particles.

21. The memory cell of claim 16, wherein the charge storage region comprises a dielectric including a plurality of trapping centers.

22. The memory cell of claim 16, wherein the energized charge carriers include light-holes.

23. The memory cell of claim 16, wherein the energized charge carriers include electrons.

24. The memory cell of claim 16, wherein the energized charge carriers include piezo-holes.

25. The memory cell of claim 16, wherein the energized charge carriers include piezo-electrons.