Integrated interconnect arrangement

• US 7,550,854 B2
• Filed: 03/19/2003
• Issued: 06/23/2009
• Est. Priority Date: 05/08/2002
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Strasser, Rudolf
• Primary Examiner(s): Parekh; Nitin
• Application Number:
  US10/514,145
• Publication Number:
  US 20060202338A1
• Time in Patent Office: 2,288 Days
• Field of Search: 257/531, 257/776, 257/664, 257/758, 257/E23.17
• US Class Current: 257/776
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

An explanation is given of an integrated interconnect arrangement having a plurality of interconnects that cross over one another at two crossover sections. By virtue of this measure, it is possible to achieve a uniform current flow in all three interconnects even at very high frequencies.

Claims

1. An integrated circuit interconnect arrangement for high frequency operation comprising:

at least three interconnects electrically connected in parallel in a plane, the electrical connection being in a direction which is transverse to a longitudinal axis of the interconnect arrangement, the at least three interconnects being connected at respective end sections;

an electrical insulating material arranged between the interconnects excluding the end sections and

at least two crossover sections arranged at different locations on the longitudinal axis of the interconnect arrangement, where the interconnects of the interconnect arrangement cross over one another at the crossover section, each interconnect being arranged to have the same length between other interconnects, each interconnect being arranged at the same length at the end sections of the interconnect arrangement wherein the interconnects are lined up transversely to the longitudinal axis of the interconnect arrangement, wherein the lined up interconnects are arranged in the plane.

2. The interconnect arrangement of claim 1, wherein the interconnects are arranged in a metallization layer between adjacent crossover sections.

3. The interconnect arrangement of claim 1, wherein at the crossover section one of the at least three interconnects is arranged transversely with respect to the other interconnects, and where, in the crossover section, the transversely arranged interconnect and the other interconnects are arranged in different metallization layers.

4. The interconnect arrangement of claim 3, wherein the other interconnects are arranged in a different direction in a crossover section than outside the crossover section.

5. The interconnect arrangement of claim 1, wherein the interconnects are arranged in different metallization layers outside the crossover sections.

6. The interconnect arrangement of claim 5, wherein at the crossover section an interconnect is arranged in a contact hole transverse to the other interconnects and the contact hole leads to a further metallization layer.

7. The interconnect arrangement of claim 6, wherein the interconnects in the crossover section are led from one metallization layer to an adjacent metallization layer.

8. The interconnect arrangement of claim 1, wherein interconnect arrangement contains two crossover sections, and wherein the interconnect arrangement has a length measured from a first end section of the interconnect arrangement to a second end section of the interconnect arrangement, and wherein one crossover section lies at one-third of the length of the interconnect arrangement and the other crossover section lies at two-thirds of the length of the interconnect arrangement.

9. The interconnect arrangement of claim 1, wherein the crossover sections are patterned identically.

10. The interconnect arrangement of claim 1, wherein the interconnect arrangement that lies outside the crossover sections are patterned identically.

11. The interconnect arrangement of claim 1, wherein each interconnect section is arranged having a same length when between other interconnects.

12. The interconnect arrangement of claim 1, wherein each interconnect section is arranged having a same length when at the end sections of the interconnect arrangement.

13. The interconnect arrangement of claim 1, wherein the interconnects are arranged such that the same amount of current flows through each interconnect.

14. The interconnect arrangement of claim 1, wherein the arrangement conducts a current with a frequency greater than about one gigahertz.

15. The interconnect arrangement of claim 1, wherein the arrangement conducts a current with a frequency greater than about fifty gigahertz.

16. The interconnect arrangement of claim 1, wherein the arrangement conducts a current with a frequency greater than about five hundred gigahertz.

17. The interconnect arrangement of claim 1, wherein a largest lateral dimension of an interconnect is less than about 10 micrometers.

18. The interconnect arrangement of claim 17, wherein a length of the interconnect arrangement is less than about 10 millimeters.

19. The interconnect arrangement of claim 1, wherein a largest lateral dimension of an interconnect is less than about 1 micrometer.

20. The interconnect arrangement of claim 19, wherein a length of the interconnect arrangement is less than about 1 millimeter.

21. The interconnect arrangement of claim 1, wherein the interconnect is a constituent part of an integrated circuit arrangement further comprising a plurality of electronic components on a semiconductor substrate.

22. The interconnect arrangement of claim 1, wherein the interconnect arrangement is formed into a coil having an inductance.

23. The interconnect arrangement of claim 1, wherein the interconnect arrangement routes signals to an antenna of a transmitting part or routes signals from a receiving part.