Configurable IC with trace buffer and/or logic analyzer functionality

• US 7,550,991 B2
• Filed: 03/13/2006
• Issued: 06/23/2009
• Est. Priority Date: 07/15/2005
• Status: Expired due to Fees

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Redgrave, Jason, Khubchandani, Teju, Hutchings, Brad
• Primary Examiner(s): Tran, Anh Q
• Application Number:
  US11/375,369
• Publication Number:
  US 20080191733A1
• Time in Patent Office: 1,198 Days
• Field of Search: 326/9, 326/14, 326/16, 326 38- 41
• US Class Current: 326/9
• CPC Class Codes: H03K 19/1731 Optimisation thereof
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits for configurably performing different operations and several user design state (UDS) circuits for storing user-design state values. The IC further includes a trace buffer for storing user-design state values associated with an operational trigger even of the IC. In some embodiments, the configurable circuits, UDS circuits, and tracer buffer are on a single IC die.

Claims

1. An integrated circuit (IC) comprising:

a) a plurality of configurable circuits for configurably performing different operations;

b) a plurality of user design state (UDS) circuits for storing user-design state values;

c) a trace buffer for storing user-design state values associated with the operation of the IC; and

d) a debug network connected to the UDS circuits and the trace buffer, the debug network for allowing the trace buffer to receive state values stored in the UDS circuits;

wherein the IC has a streaming mode that allows a plurality of the UDS circuits to be directed to repeatedly output their state values onto the debug network for storing in the trace buffer;

wherein the IC is on a single IC die.

2. The IC of claim 1 further comprising trigger detection circuitry to detect an occurrence of an operational trigger event of the IC;

wherein the trace buffer stops storing state values after the occurrence of the operational trigger event.

3. The IC of claim 1, wherein the trigger event is an event after which the trace buffer has to stop storing UDS values.

4. The IC of claim 1, wherein the trigger event is an event after which the trace buffer starts storing UDS values.

5. The IC of claim 1, wherein the IC comprises configurable circuits organized in an arrangement, and the trace buffer is positioned outside of said arrangement.

6. The IC of claim 1, wherein the IC comprises configurable circuits organized in an arrangement, and the trace buffer is positioned within said arrangement.

8. The IC of claim 1, wherein the UDS circuits include at least one memory array.

7. An integrated circuit (IC) comprising:

a) a plurality of configurable circuits for configurably performing different operations;

b) a plurality of user design state (UDS) circuits for storing user-design state values, wherein the UDS circuits comprise a plurality of configurable interconnect circuits that are configured as state elements; and

c) a trace buffer for storing user-design state values associated with the operation of the IC;

wherein the IC is on a single die.

9. A method of operating an integrated circuit (IC) with logic analyzer functionality, the IC comprising a plurality of user design state (UDS) circuits, the method comprising:

a) specifying a plurality of UDS circuits to monitor;

b) repeatedly storing state values stored by the specified UDS circuits in an on-chip trace buffer;

c) detecting an operational trigger event; and

d) terminating the storing of state values after said detecting.

10. The method of claim 9 further comprising:

a) specifying another plurality of UDS circuits to monitor; and

b) repeatedly storing the state values stored by the other specified UDS circuits in the on-chip trace buffer.

11. The method of claim 10, wherein the IC comprises a plurality of configurable circuits, wherein the specifying of the other UDS circuits and the storing of the state values stored by the other UDS circuits are performed without specifying a new configuration bit stream for configuring the configurable circuits.

12. The method of claim 9, wherein the IC comprises a debug network connected to the UDS circuits and the trace buffer, the debug network for allowing the trace buffer to receive state values stored in the UDS circuits.

13. The method of claim 12, wherein the IC has a streaming mode that allows the plurality of the UDS circuits to be specified and to be directed to repeatedly output their state values onto the debug network for storing in the trace buffer.

14. A configurable integrated circuit (IC) comprising:

a) a plurality of user design state (UDS) circuits for storing UDS values; and

b) a trace buffer for storing UDS values;

wherein the IC may be operated in a streaming mode that allows a plurality of UDS circuits to be directed to repeatedly output their UDS values for storing in the trace buffer;

wherein the configurable circuits, the UDS circuits, and the trace buffer are all on the same IC die.

15. An integrated circuit (IC) comprising:

a) a plurality of configurable circuits for configurably performing operations;

b) a plurality of user design state (UDS) circuits for storing and outputting UDS values; and

c) a trace buffer for receiving and storing a set of UDS values in the same storage location for multiple clock cycles;

wherein the configurable circuits, UDS circuits, and the trace buffer are all on a single IC die.

16. The IC of claim 15, wherein the trace buffer is further for storing said UDS values for reading at a later time.

17. The IC of claim 15, wherein the trace buffer receives UDS values from a set of UDS circuits until an operational trigger event occurs.

18. The IC of claim 17, wherein the operational trigger event is related to data generated within the IC.

19. The IC of claim 15, wherein the set of UDS values is not shifted within the trace buffer once received by the trace buffer.

20. The IC of claim 15, wherein the set of UDS values is stored in an empty storage location in the trace buffer when an empty location is available, wherein the set of UDS values is stored in a storage location storing an oldest value when no empty locations are available.

21. An integrated circuit (IC) comprising:

a) a plurality of configurable circuits for configurably performing different operations;

b) a plurality of addressable user-design state (UDS) circuits for storing and outputting state values;

c) a trace buffer for receiving and storing state values from the addressed set of UDS circuits, wherein receiving UDS values from the addressed set of UDS circuits further comprise not receiving UDS values from UDS circuits that are not in the addressed set.