Programmable logic device with on-chip nonvolatile user memory

• US 7,550,994 B1
• Filed: 01/29/2007
• Issued: 06/23/2009
• Est. Priority Date: 01/09/2004
• Status: Expired due to Term

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: White, Thomas H., Camarota, Rafael C.
• Primary Examiner(s): Barnie; Rexford
• Assistant Examiner(s): WHITE, DYLAN C
• Application Number:
  US11/668,325
• Time in Patent Office: 876 Days
• Field of Search: 326 37- 41, 326/47, 326/8, 716/16
• US Class Current: 326/38
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17772 for powering on or off

Abstract

A programmable logic integrated circuit has user-accessible nonvolatile memory for use by the programmable logic. In a specific embodiment, the programmable logic integrated circuit has a programmable logic array portion and a nonvolatile memory array portion. The nonvolatile memory array portion is segregated into a boot data part and a user data partition. The boot data partition holds data for configuring the programmable logic portion on power up, and the user data partition is for use by the programmable logic. A user can store and retrieve data from the user data partition. A built-in oscillator can be programmably connected from the nonvolatile memory portion to the PLD portion.

Claims

1. An integrated circuit comprising:

a programmable logic array portion comprising a plurality of logic array blocks configurable to implement user-defined logic functions; and

a nonvolatile memory portion coupled to the programmable logic array portion, wherein the nonvolatile memory portion comprises;

a boot data partition to store configuration data;

a user data partition to store information to be accessed by an application running on the programmable logic array portion;

a first data port for data read access to the boot data partition; and

a second data port for data read access to the user data partition.

2. The integrated circuit of claim 1 wherein the programmable logic array portion further comprises volatile memory elements and programmable interconnect, wherein the logic array blocks and programmable interconnect are configurable using the volatile memory elements.

3. The integrated circuit of claim 1 further comprising:

an interface block coupled between the programmable logic portion and the nonvolatile memory portion, the interface block to read information from the user data partition of the nonvolatile memory portion and to write information to the user data partition of the nonvolatile memory.

4. The integrated circuit of claim 3 wherein the interface block provides at least one of an SPI serial data interface, I2C serial data interface, 3-wire serial data interface, 2-wire serial data interface, or parallel data interface to the nonvolatile memory portion.

5. The integrated circuit of claim 3 wherein the interface block comprises:

a first block providing an SPI serial data interface;

a second block providing an I2C serial data interface;

a third block providing a 3-wire serial data interface;

a first multiplexer configurable to select one of the first, second, or third block to a port of the nonvolatile memory portion; and

a second multiplexer configurable to select one of the first, second, or third block to the programmable logic array portion.

6. The integrated circuit of claim 5 further comprising:

a fourth block providing a 2-wire serial data interface; and

a fifth block providing a parallel data interface,

wherein the first multiplexer is configurable to select one of the first, second, third, fourth, or fifth blocks to a part of the nonvolatile memory portion, and

wherein the second multiplexer is configurable to select one of the first, second, third, fourth, of fifth blocks to the programmable logic array portion.

7. The integrated circuit of claim 1 wherein the information is selected from the group consisting of network parameters, address book, and telephone number information.

8. An integrated circuit comprising:

a programmable logic array portion comprising a plurality of logic array blocks configurable to implement user-defined logic functions;

a nonvolatile memory portion coupled to the programmable logic array portion, wherein the nonvolatile memory portion comprises;

a boot data partition to store configuration data;

a user data partition to store user data;

a first data port for data read access to the boot data partition; and

a second data port for data read access to the user data partition; and

an oscillator circuit coupled to the programmable logic array portion and the nonvolatile memory portion, wherein the oscillator circuit comprises an enable input for enabling and disabling the oscillator circuit,

wherein a signal provided by the oscillator circuit clocks transfers of user data from the nonvolatile memory portion to the programmable array portion, and

wherein the programmable logic array portion further comprises volatile memory elements and programmable interconnect, wherein the logic array blocks and programmable interconnect are configurable using the volatile memory elements.

9. The integrated circuit of claim 8 further comprising:

an interface block coupled between the programmable logic portion and the nonvolatile memory portion, the interface block to read data from the user data partition of the nonvolatile memory portion and to write data to the user data partition of the nonvolatile memory.

10. The integrated circuit of claim 9 wherein the interface block provides at least one of an SPI serial data interface, I2C serial data interface, 3-wire serial data interface, 2-wire serial data interface, or parallel data interface to the nonvolatile memory portion.

11. An integrated circuit comprising:

a programmable logic array portion comprising a plurality of logic array blocks configurable to implement user-defined logic functions;

a nonvolatile memory portion coupled to the programmable logic array portion, wherein the nonvolatile memory portion comprises;

a boot data partition to store configuration data;

a user data partition to store user data;

a first data port for data read access to the boot data partition; and

a second data port for data read access to the user data partition; and

an interface block coupled between the programmable logic portion and the nonvolatile memory portion, the interface block to read data from the user data partition of the nonvolatile memory portion and to write data to the user data partition of the nonvolatile memory, wherein the interface block comprises;

a shift register circuit comprising inputs coupled to the programmable logic array portion;

a data register circuit comprising inputs coupled to the programmable logic array portion, and input and outputs coupled to the nonvolatile memory portion; and

a program/erase control circuit comprising inputs coupled to the programmable logic array portion, and an output coupled to the nonvolatile memory portion.

12. An integrated circuit comprising:

a programmable logic array portion comprising a plurality of logic array blocks configurable to implement user-defined logic functions; and

a nonvolatile memory portion coupled to the programmable logic array portion, wherein the nonvolatile memory portion comprises;

a boot data partition to store configuration data;

a user data partition to store user data;

a first data port for data read access to the boot data partition; and

a second data port for data read access to the user data partition,

wherein the nonvolatile memory portion further comprises;

a first memory cell for storing a first security bit and a second memory cell for storing a second security bit,

wherein when the first security bit is in a first state, data stored in the boot data partition may be transferred through a third data port of the nonvolatile memory portion to pins of the integrated circuit,

when the first security bit is in a second state, data stored in the boot data partition is prevented from being transferred through the third data port to pins of the integrated circuit,

when the second security bit is in a first state, data stored in the user data partition may be transferred through the third port to pins of the integrated circuit, and

when the second security bit is in a second state, data stored in the user data partition is prevented from being transferred through the third port to pins of the integrated circuit.

13. A method of operating an integrated circuit comprising:

enabling a clock enable signal to activate an oscillator coupled to a nonvolatile memory portion of the integrated circuit; and

during a normal operation mode, transferring user data stored in a user data partition of the nonvolatile memory portion to a volatile memory portion of a programmable logic array portion of the integrated circuit to be accessed by the programmable logic array portion, wherein a signal provided by the oscillator clocks transfers of the user data from the nonvolatile memory portion to the programmable array portion.

14. The method of claim 13 further comprising:

before entering the normal mode, providing power to the programmable integrated circuit; and

transferring configuration data from the nonvolatile memory portion of the programmable integrated circuit through a read-only port of the nonvolatile memory portion to a programmable logic array portion to configure the programmable logic array portion.

15. The method of claim 13 further comprising:

setting a first security bit to prevent output of the configuration data via pins of the programmable integrated circuit.

16. The method of claim 15 further comprising:

setting a second security bit to prevent output of the data in the user data partition via pins of the programmable integrated circuit.

17. An integrated circuit comprising:

a programmable logic array portion comprising logic array blocks configurable to implement user-defined logic functions;

a nonvolatile memory portion coupled to the programmable logic array portion, wherein the nonvolatile memory portion comprises;

a boot data partition to store configuration data; and

a user data partition to store user data for an operational mode where the user functions are being utilized;

a first memory cell for storing a first security bit, wherein when the first security bit is in a first state, data stored in the boot data partition may be transferred to pins of the integrated circuit, and when the first security bit is in a second state, data stored in the boot data partition is prevented from being transferred to pins of the integrated circuit; and

a second memory cell for storing a second security bit, wherein when the second security bit is in a first state, data stored in the user data partition may be transferred to pins of the integrated circuit, and when the second security bit is in a second state, data stored in the user data partition is prevented from being transferred to pins of the integrated circuit.

18. The integrated circuit of claim 17 wherein the boot data partition is accessible through a first port and the user data partition is accessible though a second port.

19. The integrated circuit of claim 17 further comprising:

an oscillator circuit coupled to the programmable logic array portion and nonvolatile memory portion, wherein the oscillator circuit comprises an enable input for enabling and disabling the oscillator circuit.

20. The integrated circuit of claim 17 wherein the boot data partition is accessible to the programmable logic array portion through the first port and the user data partition is accessible to a user though a second port.

21. The integrated circuit of claim 17 wherein the programmable logic array portion further comprises volatile memory elements and a programmable interconnect, wherein the logic array blocks and programmable interconnect are configurable using the volatile memory elements to implement user functions.

22. The integrated circuit of claim 17 wherein the oscillator circuit is used in clocking data transferred between the programmable logic array portion and the nonvolatile memory portion.

23. The integrated circuit of claim 17 wherein the oscillator circuit is used to clock data transferred within the programmable logic array portion of the integrated circuit.

24. The integrated circuit of claim 17 wherein an output of the oscillator circuit is programmably coupled to a pin of the integrated circuit.

25. An integrated circuit comprising:

a programmable portion;

a nonvolatile memory portion;

a volatile memory portion coupled to the nonvolatile memory portion and the programmable portion, wherein the integrated circuit is configurable by user data stored in the volatile memory portion; and

an oscillator circuit coupled to the volatile memory portion and the nonvolatile memory portion wherein the oscillator circuit comprises an enable input for enabling and disabling the oscillator circuit and wherein a signal provided by the oscillator circuit clocks transfers of the user data from the nonvolatile memory portion to the volatile memory portion.

26. The integrated circuit of claim 25 wherein the programmable portion comprises logic array blocks and programmable interconnect, wherein the logic array blocks and programmable interconnect are configurable using the volatile memory portion.

27. An integrated circuit comprising:

a programmable portion;

a volatile memory portion coupled to the programmable portion;

a nonvolatile memory portion; and

an interface block coupled between the volatile memory portion and the nonvolatile memory portion, the interface block to read user data from and to write user data to the nonvolatile memory, wherein the interface block comprises;

a shift register circuit comprising inputs coupled to the volatile memory portion;

a data register circuit comprising inputs coupled to the volatile memory portion, and input and outputs coupled to the nonvolatile memory portion; and

a program/erase control circuit comprising inputs coupled to the volatile memory portion, and an output coupled to the nonvolatile memory portion.

28. An integrated circuit comprising:

a programmable portion;

a nonvolatile memory comprising a boot data partition to store configuration data for the programmable portion, a user data partition to store user data, a first memory cell for storing a first security bit, a second memory cell for storing a second security bit and a data port,

wherein when the first security bit is in a first state, data stored in the boot data partition may be transferred through the data port to pins of the integrated circuit,

when the first security bit is in a second state, data stored in the boot data partition is prevented from being transferred through the data port to pins of the integrated circuit,

when the second security bit is in a first state, data stored in the user data partition may be transferred through the data port to pins of the integrated circuit, and

when the second security bit is in a second state, data stored in the user data partition is prevented from being transferred through the data port to pins of the integrated circuit.