Enhanced output impedance compensation
First Claim
1. A compensation circuit for compensating an output impedance of at least a first metal-oxide-semiconductor (MOS) device over variations in at least one of process, supply voltage and temperature conditions to which the at least first MOS device may be subjected, the compensation circuit comprising:
- a first current source operative to generate a first current having a value which is substantially constant;
a second current source operative to generate a second current having a value which is programmable as a function of at least one control signal presented to the second current source;
a comparator connected to respective outputs of the first and second current sources, the comparator being operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current; and
a processor connected in a feedback arrangement between the comparator and the second current source, the processor receiving the output signal generated by the comparator and generating the at least one control signal as a function of the output signal, the processor being operative to control the value of the second current so that the second current is substantially equal to the first current, whereby the at least one control signal generated by the processor is adapted to compensate the output impedance of the at least first MOS device over variations in at least one of process, supply voltage and temperature conditions to which the at least first MOS device may be subjected;
wherein the second current source comprises;
a reference source generating a voltage which is proportional to a supply voltage of the compensation circuit;
a voltage clamp operative to clamp the voltage generated by the reference source across at least a second MOS device, a gate of the at least second MOS device receiving the at least one control signal, the at least second MOS device being substantially matched to the at least first MOS device to be compensated; and
a current mirror circuit operative to generate the second current, the second current being substantially matched to a current flowing through the at least second MOS device.
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Accused Products
Abstract
A compensation circuit for compensating an output impedance of at least a first MOS device over PVT variations to which the first MOS device may be subjected includes a first current source generating a first current having a value which is substantially constant and a second current source generating a second current having a value which is programmable as a function of at least one control signal presented to the second current source. A comparator is connected to respective outputs of the first and second current sources and is operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current. A processor connected in a feedback arrangement between the comparator and the second current source receives the output signal generated by the comparator and generates the control signal for controlling the second current as a function of the output signal. The processor is operative to control the value of the second current so that the second current is substantially equal to the first current.
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Citations
20 Claims
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1. A compensation circuit for compensating an output impedance of at least a first metal-oxide-semiconductor (MOS) device over variations in at least one of process, supply voltage and temperature conditions to which the at least first MOS device may be subjected, the compensation circuit comprising:
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a first current source operative to generate a first current having a value which is substantially constant; a second current source operative to generate a second current having a value which is programmable as a function of at least one control signal presented to the second current source; a comparator connected to respective outputs of the first and second current sources, the comparator being operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current; and a processor connected in a feedback arrangement between the comparator and the second current source, the processor receiving the output signal generated by the comparator and generating the at least one control signal as a function of the output signal, the processor being operative to control the value of the second current so that the second current is substantially equal to the first current, whereby the at least one control signal generated by the processor is adapted to compensate the output impedance of the at least first MOS device over variations in at least one of process, supply voltage and temperature conditions to which the at least first MOS device may be subjected; wherein the second current source comprises; a reference source generating a voltage which is proportional to a supply voltage of the compensation circuit; a voltage clamp operative to clamp the voltage generated by the reference source across at least a second MOS device, a gate of the at least second MOS device receiving the at least one control signal, the at least second MOS device being substantially matched to the at least first MOS device to be compensated; and a current mirror circuit operative to generate the second current, the second current being substantially matched to a current flowing through the at least second MOS device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16)
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13. A compensation circuit for compensating an output impedance of at least a first metal-oxide-semiconductor (MOS) device over variations in at least one of process, supply voltage and temperature conditions to which the at least first MOS device may be subjected, the compensation circuit comprising:
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a first current source operative to generate a first current having a value which is substantially constant; a second current source operative to generate a second current having a value which is programmable as a function of at least one control signal presented to the second current source; a comparator connected to respective outputs of the first and second current sources, the comparator being operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current; and a processor connected in a feedback arrangement between the comparator and the second current source, the processor receiving the output signal generated by the comparator and generating the at least one control signal as a function of the output signal, the processor being operative to control the value of the second current so that the second current is substantially equal to the first current; wherein the processor is operative;
(i) to set the at least one control signal to a logic low level and to check if the output signal generated by the comparator is a low level;
(ii) to set the at least one control signal to a logic high level and to determine if the output signal generated by the comparator is a high level;
(iii) to set the at least one control signal to a midpoint between the low and high levels in steps (i) and (ii) and determine whether the output signal is high, indicating that a desired setting for the at least one control signal lies in a lower half of a range between the low and high levels, or whether the output signal is low, indicating that the desired setting for the at least one control signal lies in an upper half of the range between the low and high levels;
(iv) to set the at least one control signal to a midpoint of the lower or upper half, depending on the comparator output in step (iii); and
(v) repeat steps (iii) and (iv) until consecutive bit states are detected which cannot be divided further.
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17. An integrated circuit including at least one compensation circuit for compensating an output impedance of at least a first metal-oxide-semiconductor (MOS) device over variations in at least one of process, supply voltage and temperature conditions to which the at least first MOS device may be subjected, the at least one compensation circuit comprising:
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a first current source operative to generate a first current having a value which is substantially constant; a second current source operative to generate a second current having a value which is programmable as a function of at least one control signal presented to the second current source; a comparator connected to respective outputs of the first and second current sources, the comparator being operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current; and a processor connected in a feedback arrangement between the comparator and the second current source, the processor receiving the output signal generated by the comparator and generating the at least one control signal as a function of the output signal, the processor being operative to control the value of the second current so that the second current is substantially equal to the first current, whereby the at least one control signal generated by the processor is adapted to compensate the output impedance of the at least first MOS device over variations in at least one of process, supply voltage and temperature conditions to which the at least first MOS device may be subjected; wherein the second current source comprises; a reference source generating a voltage which is proportional to a supply voltage of the compensation circuit; a voltage clamp operative to clamp the voltage generated by the reference source across at least a second MOS device, a gate of the at least second MOS device receiving the at least one control signal, the at least second MOS device being substantially matched to the at least first MOS device to be compensated; and a current mirror circuit operative to generate the second current, the second current being substantially matched to a current flowing through the at least second MOS device. - View Dependent Claims (18)
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19. An integrated circuit including at least one compensation circuit for compensating an output impedance of at least a first metal-oxide-semiconductor (MOS) device over variations in at least one of process, supply voltage and temperature conditions to which the at least first MOS device may be subjected, the at least one compensation circuit comprising:
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a first current source operative to generate a first current having a value which is substantially constant; a second current source operative to generate a second current having a value which is programmable as a function of at least one control signal presented to the second current source; a comparator connected to respective outputs of the first and second current sources, the comparator being operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current; and a processor connected in a feedback arrangement between the comparator and the second current source, the processor receiving the output signal generated by the comparator and generating the at least one control signal as a function of the output signal, the processor being operative to control the value of the second current so that the second current is substantially equal to the first current; wherein the processor is operative;
(i) to set the at least one control signal to a logic low level and to check if the output signal generated by the comparator is a low level;
(ii) to set the at least one control signal to a logic high level and to determine if the output signal generated by the comparator is a high level;
(iii) to set the at least one control signal to a midpoint between the low and high levels in steps (i) and (ii) and determine whether the output signal is high, indicating that a desired setting for the at least one control signal lies in a lower half of a range between the low and high levels, or whether the output signal is low, indicating that the desired setting for the at least one control signal lies in an upper half of the range between the low and high levels;
(iv) to set the at least one control signal to a midpoint of the lower or upper half, depending on the comparator output in step (iii); and
(v) repeat steps (iii) and (iv) until consecutive bit states are detected which cannot be divided further.
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20. A method for compensating an output impedance of at least a first metal-oxide-semiconductor (MOS) device over variations in at least one of process, supply voltage and temperature conditions to which the at least first MOS device may be subjected, the method comprising the steps of:
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generating a first current having a value which is substantially constant; generating a second current having a value which is programmable as a function of at least one control signal; measuring a difference between the respective values of the first and second currents and generating an output signal indicative of relative magnitudes of the first current and the second current; generating the at least one control signal as a function of the output signal and controlling the value of the second current so that the second current is substantially equal to the first current; and applying the at least one control signal to the at least first MOS device to thereby compensate the output impedance of the at least first MOS device over variations in at least one of process, supply voltage and temperature conditions to which the at least first MOS device may be subjected.
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Specification