Systems and methods for pipelined analog to digital conversion
First Claim
1. An analog to digital converter, wherein the analog to digital converter comprises:
- a residue amplifier, wherein the residue amplifier is associated with a first capacitance set that includes a first feedback capacitor and first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and second set of input capacitors, wherein the first capacitance set is separately switched from the second capacitance set, and wherein a portion of a clock cycle is provided for charging the first set of input capacitors, and a full clock cycle is provided for settling the residue amplifier.
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Abstract
Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide methods for performing analog to digital conversions that include providing an analog to digital converter with a residue amplifier that is associated with a first capacitance set that includes a first feedback capacitor and first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and second set of input capacitors. The methods further include performing a first sample of an analog input voltage by charging the first set of input capacitors from the analog voltage input during a first period; amplifying the first sample during a second period; performing a second sample of the analog input voltage by charging the second set of input capacitors from the analog voltage input during a third period; and amplifying the second sample during a fourth period.
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Citations
22 Claims
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1. An analog to digital converter, wherein the analog to digital converter comprises:
a residue amplifier, wherein the residue amplifier is associated with a first capacitance set that includes a first feedback capacitor and first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and second set of input capacitors, wherein the first capacitance set is separately switched from the second capacitance set, and wherein a portion of a clock cycle is provided for charging the first set of input capacitors, and a full clock cycle is provided for settling the residue amplifier. - View Dependent Claims (2, 3, 4, 5, 6, 22)
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7. A method for performing an analog to digital conversion, the method comprising:
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providing an analog to digital converter, wherein the analog to digital converter includes a residue amplifier associated with a first capacitance set that includes a first feedback capacitor and first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and second set of input capacitors; performing a first sample of an analog input voltage by charging the first set of input capacitors from the analog voltage input during a first period; amplifying the first sample during a second period; performing a second sample of the analog input voltage by charging the second set of input capacitors from the analog voltage input during a third period; amplifying the second sample during a fourth period; and wherein the first period overlaps the fourth period, and wherein the third period overlaps the second period. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. An analog to digital converter, wherein the analog to digital converter includes:
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a residue amplifier, wherein the residue amplifier is associated with a first capacitance set that includes a first feedback capacitor and first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and second set of input capacitors, and wherein the first capacitance set is separately switched from the second capacitance set; and a sub-adc, wherein an output from the sub-adc controls a first value subtraction from a first value maintained on the first set of input capacitors to create a first residue value, and a second value subtraction from a second value maintained on the second set of input capacitors to create a second residue value. - View Dependent Claims (16, 17, 18)
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19. A pipelined analog to digital converter, wherein the pipelined analog to digital converter comprises:
a residue amplifier, wherein the residue amplifier is associated with a first capacitance set that includes a first feedback capacitor and first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and second set of input capacitors, wherein the first capacitance set is separately switched from the second capacitance set, and wherein the residue amplifier is shared between two pipeline stages.
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20. An analog to digital converter, wherein the analog to digital converter comprises:
a residue amplifier, wherein the residue amplifier is associated with a first capacitance set that includes a first feedback capacitor and a first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and a second set of input capacitors, wherein the first capacitance set is separately switched from the second capacitance set, wherein the first set of input capacitors are electrically coupled to an analog voltage input during a first period, wherein the second set of input capacitors are electrically coupled to the residue amplifier during the first period, wherein the second set of input capacitors are electrically coupled to the analog voltage input during a second period, and wherein the second set of input capacitors are electrically coupled to the residue amplifier during the second period. - View Dependent Claims (21)
Specification