Non-volatile semiconductor memory with page erase

• US 7,551,492 B2
• Filed: 03/08/2007
• Issued: 06/23/2009
• Est. Priority Date: 03/29/2006
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki
• Primary Examiner(s): Lam; David
• Application Number:
  US11/715,838
• Publication Number:
  US 20070230253A1
• Time in Patent Office: 838 Days
• Field of Search: 365/185.29, 365/185.17, 365/185.18, 365/185.27, 365/185.23, 365/185.12
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A substrate voltage is applied to the substrate of the selected block. A common select voltage may be applied to each selected wordline and the common unselect voltage may be applied to each unselected wordline. Select and unselect voltages may be applied to any of the wordlines of a select block. A page erase verify operation may be applied to a block having plural erased pages and plural nonerased pages.

Claims

1. A method of erasing a page in a nonvolatile memory array having plural strings of memory cells on a substrate, wordlines across the strings to pages of memory cells and a pass transistor applying a voltage to each wordline, the method comprising:

enabling each pass transistor of a selected block;

at each of the plural selected wordlines of the selected block, applying a common select voltage to the pass transistor;

at each of plural unselected wordlines of the selected block, applying a common unselect voltage to the pass transistor; and

applying a substrate voltage to the substrate of the selected block, the voltage difference between the substrate voltage and a resulting voltage of each selected wordline causing the page of memory cells of the selected wordline to erase, and the voltage difference between the substrate voltage and a resulting voltage of each unselected wordline being less than that which erases the page of memory cells of the unselected wordline.

2. A method as recited in claim 1 wherein the select voltage and the unselect voltage are applied to the pass transistors of the selected block though a wordline decoder adapted to apply the select voltage to any of the pass transistors as the unselect voltage is applied to any other pass transistor.

3. A method as recited in claim 1 wherein the selected wordlines include selected wordlines separated by at least one unselected wordline.

4. A method as recited in claim 1 wherein the unselected wordlines include unselected wordlines separated by at least one selected wordline.

5. A method as recited in claim 1 wherein the resulting voltage of each selected wordline is substantially the same as the select voltage and the resulting voltage of each unselected wordline is substantially the same as the unselect voltage.

6. A method as recited in claim 1 wherein the select voltage is about zero volts and the unselect voltage is about equal to the applied substrate voltage.

7. A method as recited in claim 1 wherein the resulting voltage of each selected wordline is substantially the same as the select voltage and the resulting voltage of each unselected wordline is a floating voltage coupled from the unselect voltage toward the substrate voltage.

8. A method as recited in claim 7 wherein a common gate signal to each pass transistor of the selected block has a value V2, the unselect voltage is greater than V2 and the unselected wordline precharges to V2−

Vtn, and wherein V2 is substantially less than the applied substrate voltage.

9. A method as recited in claim 8 wherein V2 is at least 50% of the applied substrate voltage.

10. A method as recited in claim 8 wherein, in an unselected block, all pass transistors to wordlines are gated off after a voltage less than the unselect voltage is applied to each pass transistor and the wordlines float to prevent erasure.

11. A method as recited in claim 1 wherein the unselect voltage is closer to the voltage applied to the substrate than to the select voltage.

12. A method of erasing a page in a nonvolatile memory array having plural strings of memory cells on a substrate, wordlines across the strings to pages of memory cells and a pass transistor applying a voltage to each wordline, the method comprising:

enabling each pass transistor of a selected block;

at each of at least one selected wordline of the selected block, applying a select voltage to the pass transistor;

at each of at least one unselected wordline of the selected block, applying an unselect voltage to the pass transistor; and

applying a substrate voltage to the substrate of the selected block, the unselect voltage being closer to the applied substrate voltage than to the select voltage, the voltage difference between the substrate voltage and a resulting voltage of each selected wordline causing the page of memory cells of the selected wordline to erase, and the voltage difference between the substrate voltage and a resulting voltage of each unselected wordline being less than that which erases the page of memory cells of the unselected wordline.

13. A method as recited in claim 12 wherein the select voltage and the unselect voltage are applied to the pass transistors of the selected block though a wordline decoder adapted to apply the select voltage to any of the pass transistors as the unselect voltage is applied to any other pass transistor.

14. A method as recited in claim 12 wherein the selected wordlines include selected wordlines separated by at least one unselected wordline.

15. A method as recited in claim 12 wherein the unselected wordlines include unselected wordlines separated by at least one selected wordline.

16. A method as recited in claim 12 wherein the resulting voltage of each selected wordline is substantially the same as the select voltage and the resulting voltage of each unselected wordline is substantially the same as the unselect voltage.

17. A method as recited in claim 12 wherein the select voltage is about zero volts and the unselect voltage is about equal to the applied substrate voltage.

18. A method as recited in claim 12 wherein the resulting voltage of each selected wordline is substantially the same as the select voltage and the resulting voltage of each unselected wordline is a floating voltage coupled from the unselect voltage toward the substrate voltage.

19. A method as recited in claim 18 wherein a common gate signal to each pass transistor of the selected block has a value V2, the unselect voltage is greater than V2 and the unselected wordline precharges to V2−

Vtn, and wherein V2 is substantially less than the applied substrate voltage.

20. A method as recited in claim 19 wherein V2 is at least 50% of the applied substrate voltage.

21. A method as recited in claim 19 wherein, in an unselected block, all pass transistors to wordlines are gated off after a voltage less than the unselect voltage is applied to each pass transistor and the wordlines float to prevent erasure.

22. A method of erasing a page in a nonvolatile memory array having plural strings of memory cells on a substrate, wordlines across the strings to pages of memory cells and a pass transistor applying a voltage to each wordline, the method comprising:

enabling each pass transistor of a selected block;

through a wordline decoder adapted to apply a select voltage to any of the pass transistors and to apply an unselected voltage to any other of the pass transistors;

at each of plural selected wordlines of the selected block, applying the select voltage to the pass transistor; and

at each of plural unselected wordlines of the selected block, applying the unselect voltage to the pass transistor; and

applying a substrate voltage to the substrate of the selected block, the voltage difference between the substrate voltage and a resulting voltage of each selected wordline causing the page of memory cells of the selected wordline to erase, and the voltage difference between the substrate voltage and a resulting voltage of each unselected wordline being less than that which erases the page of memory cells of the unselected wordline.

23. A method as recited in claim 22 wherein the selected wordlines include selected wordlines separated by at least one unselected wordline.

24. A method as recited in claim 22 wherein the unselected wordlines include unselected wordlines separated by at least one selected wordline.

25. A method as recited in claim 22 wherein the resulting voltage of each selected wordline is substantially the same as the select voltage and the resulting voltage of each unselected wordline is substantially the same as the unselect voltage.

26. A method as recited in claim 22 wherein the select voltage is about zero volts and the unselect voltage is about equal to the applied substrate voltage.

27. A method as recited in claim 22 wherein the resulting voltage of each selected wordline is substantially the same as the select voltage and the resulting voltage of each unselected wordline is a floating voltage coupled from the unselect voltage toward the substrate voltage.

28. A method as recited in claim 27 wherein a common gate signal to each pass transistor of the selected block has a value V2, the unselect voltage is greater than V2 and the unselected wordline precharges to V2−

Vtn, and wherein V2 is substantially less than the applied substrate voltage.

29. A method as recited in claim 28 wherein V2 is at least 50% of the applied substrate voltage.

30. A method as recited in claim 28 wherein, in an unselected block, all pass transistors to wordlines are gated off after a voltage less than the unselect voltage is applied to each pass transistor and the wordlines float to prevent erasure.

31. A method as recited in claim 22 wherein the unselect voltage is closer to the voltage applied to the substrate than to the select voltage.

32. A nonvolatile memory comprising:

a memory array comprising plural strings of memory cells on a substrate and wordlines across the strings to pages of memory cells;

a pass transistor to each wordline;

a block decoder that enables each pass transistor in a selected block during an erase operation;

a substrate voltage source that applies an erase voltage to the substrate during the erase operation; and

a wordline decoder that applies a common select voltage to each pass transistor of a page to be erased in the selected block and a common unselect voltage to each wordline of each other page in the selected block, the wordline decoder responding to address instructions to apply the select voltage to plural wordlines of the selected block and to apply the unselect voltage to plural wordlines of the selected block.

33. A memory as recited in claim 32, wherein the wordline decoder is adapted to apply the select voltage to any of the wordlines and the unselect voltage to any of the wordlines.

34. A memory as recited in claim 32 wherein a resulting voltage of each selected wordline is substantially the same as the select voltage and a resulting voltage of each unselected wordline is substantially the same as the unselect voltage.

35. A memory as recited in claim 32 wherein the select voltage is about zero volts and the unselect voltage is about equal to the voltage.

36. A memory as recited in claim 32 wherein a resulting voltage of each selected wordline is substantially the same as the select voltage and a resulting voltage of each unselected wordline is a floating voltage coupled from the unselect voltage toward the erase voltage.

37. A memory as recited in claim 36 wherein a common gate signal to each pass transistor of the selected block has a value V2, the unselect voltage is greater than V2 and the unselected wordline precharges to V2−

Vtn, and wherein V2 is substantially less than the applied substrate voltage.

38. A memory as recited in claim 37 wherein V2 is at least 50% of the erase voltage.

39. A memory as recited in claim 37 wherein, in an unselected block, all pass transistors to wordlines are gated off after a voltage less than the unselect voltage is applied to each pass transistor and the wordlines float to prevent erasure.

40. A memory as recited in claim 32 wherein the unselect voltage is closer to the erase voltage applied to the substrate than to the select voltage.

41. A nonvolatile memory comprising:

a memory array comprising plural strings of memory cells on a substrate and wordlines across the strings to pages of memory cells;

a pass transistor to each wordline;

a block decoder that enables each pass transistor in a selected block during an erase operation;

a substrate voltage source that applies an erase voltage to the substrate during the erase operation; and

a wordline decoder that applies a select voltage to each pass transistors of a page to be erased in the selected block and an unselect voltage to each wordline of each other page in the selected block, the unselect voltage being closer to the erase voltage than to the select voltage.

42. A memory as recited in claim 41, wherein the wordline decoder is adapted to apply the select voltage to any of the wordlines and the unselect voltage to any of the wordlines.

43. A memory as recited in claim 41 wherein a resulting voltage of each selected wordline is substantially the same as the select voltage and a resulting voltage of each unselected wordline is substantially the same as the unselect voltage.

44. A memory as recited in claim 41 wherein the select voltage is about zero volts and the unselect voltage is about equal to the voltage.

45. A memory as recited in claim 41 wherein a resulting voltage of each selected wordline is substantially the same as the select voltage and a resulting voltage of each unselected wordline is a floating voltage coupled from the unselect voltage toward the erase voltage.

46. A memory as recited in claim 45 wherein a common gate signal to each pass transistor of the selected block has a value V2, the unselect voltage is greater than V2 and the unselected wordline precharges to V2−

Vtn, and wherein V2 is substantially less than the applied substrate voltage.

47. A memory as recited in claim 46 wherein V2 is at least 50% of the erase voltage.

48. A memory as recited in claim 46 wherein, in an unselected block, all pass transistors to wordlines are gated off after a voltage less than the unselect voltage is applied to each pass transistor and the wordlines float to prevent erasure.

49. A nonvolatile memory comprising:

a memory array comprising plural strings of memory cells on a substrate and wordlines across the strings to pages of memory cells;

a pass transistor to each wordline;

a block decoder that enables each pass transistor in a selected block during an erase operation;

a substrate voltage source that applies an erase voltage to the substrate during the erase operation; and

a wordline decoder adapted to apply a select voltage to each pass transistor of any page to be erased in the selected block and a common unselect voltage to any wordline of each other page in the selected block, the wordline decoder responding to address instructions to apply the select voltage to plural wordlines of the selected block and to apply the unselect voltage to plural wordlines of the selected block.

50. A memory as recited in claim 49 wherein a resulting voltage of each selected wordline is substantially the same as the select voltage and a resulting voltage of each unselected wordline is substantially the same as the unselect voltage.

51. A memory as recited in claim 49 wherein the select voltage is about zero volts and the unselect voltage is about equal to the voltage.

52. A memory as recited in claim 49 wherein a resulting voltage of each selected wordline is substantially the same as the select voltage and a resulting voltage of each unselected wordline is a floating voltage coupled from the unselect voltage toward the erase voltage.

53. A memory as recited in claim 52 wherein a common gate signal to each pass transistor of the selected block has a value V2, the unselect voltage is greater than V2 and the unselected wordline precharges to V2−

Vtn, and wherein V2 is substantially less than the applied substrate voltage.

54. A memory as recited in claim 53 wherein V2 is at least 50% of the erase voltage.

55. A memory as recited in claim 53 wherein, in an unselected block, all pass transistors to wordlines are gated off after a voltage less than the unselect voltage is applied to each pass transistor and the wordlines float to prevent erasure.

56. A memory as recited in claim 49 wherein the unselect voltage is closer to the erase voltage applied to the substrate than to the select voltage.