×

Non-volatile semiconductor memory with page erase

  • US 7,551,492 B2
  • Filed: 03/08/2007
  • Issued: 06/23/2009
  • Est. Priority Date: 03/29/2006
  • Status: Active Grant
First Claim
Patent Images

1. A method of erasing a page in a nonvolatile memory array having plural strings of memory cells on a substrate, wordlines across the strings to pages of memory cells and a pass transistor applying a voltage to each wordline, the method comprising:

  • enabling each pass transistor of a selected block;

    at each of the plural selected wordlines of the selected block, applying a common select voltage to the pass transistor;

    at each of plural unselected wordlines of the selected block, applying a common unselect voltage to the pass transistor; and

    applying a substrate voltage to the substrate of the selected block, the voltage difference between the substrate voltage and a resulting voltage of each selected wordline causing the page of memory cells of the selected wordline to erase, and the voltage difference between the substrate voltage and a resulting voltage of each unselected wordline being less than that which erases the page of memory cells of the unselected wordline.

View all claims
  • 13 Assignments
Timeline View
Assignment View
    ×
    ×